On Tue, 2025-07-22 at 09:59 -0300, Gustavo Sousa wrote:
> Quoting Jouni Högander (2025-07-22 09:56:18-03:00)
> > According to C10 VDR Register programming sequence we need set
> > C10_VDR_CTRL_MSGBUS_ACCESS before accessing PHY internal registers
> > from
> > MsgBus.
> >
> > v2: set C10_VDR_CTRL_MSGBUS_ACCESS once for all owned lanes
> >
> > Bspec: 68962
> > Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure
> > LFPS sending")
> > Suggested-by: Gustavo Sousa <gustavo.so...@intel.com>
> > Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
>
> Reviewed-by: Gustavo Sousa <gustavo.so...@intel.com>
Whole set now pushed to drm-intel-next. Thank you Gustavo for providing
review support on this.
BR,
Jouni Högander
>
> > ---
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index a203937d66db..801235a5bc0a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3251,6 +3251,10 @@ void intel_lnl_mac_transmit_lfps(struct
> > intel_encoder *encoder,
> >
> > wakeref = intel_cx0_phy_transaction_begin(encoder);
> >
> > + if (intel_encoder_is_c10phy(encoder))
> > + intel_cx0_rmw(encoder, owned_lane_mask,
> > PHY_C10_VDR_CONTROL(1), 0,
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> > MB_WRITE_COMMITTED);
> > +
> > for (i = 0; i < 4; i++) {
> > int tx = i % 2 + 1;
> > u8 lane_mask = i < 2 ? INTEL_CX0_LANE0 :
> > INTEL_CX0_LANE1;
> > --
> > 2.43.0
> >
