On Tue, 2025-07-29 at 15:46 +0300, Vinod Govindapillai wrote:
> As per the wa_18038517565, we need to disable FBC compressor
> clock gating before enabling FBC and enable after disabling
> FBC. Placing the enabling of clock gating in the fbc deactivate
> function can make the above wa logic go wrong in case of
> frontbuffer rendering FBC mechanism. FBC deactivate can get
> called during fb invalidate and then the corresponding FBC
> activate can get called without properly disabling the clock
> gating and can result in compression stalled. So move the
> enable clock gating at the end of one FBC session after FBC
> is completely disabled for a pipe.
Reviewed-by: Jouni Högander <jouni.hogan...@intel.com>
>
> Bspec: 74212, 72197, 69741, 65555
> Fixes: 010363c46189 ("drm/i915/display: implement wa_18038517565")
> Signed-off-by: Vinod Govindapillai <vinod.govindapil...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index e2e03af520b2..f82d392f1e22 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -552,10 +552,6 @@ static void ilk_fbc_deactivate(struct intel_fbc
> *fbc)
> if (dpfc_ctl & DPFC_CTL_EN) {
> dpfc_ctl &= ~DPFC_CTL_EN;
> intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
> dpfc_ctl);
> -
> - /* wa_18038517565 Enable DPFC clock gating after FBC
> disable */
> - if (display->platform.dg2 || DISPLAY_VER(display) >=
> 14)
> - fbc_compressor_clkgate_disable_wa(fbc,
> false);
> }
> }
>
> @@ -1710,6 +1706,10 @@ static void __intel_fbc_disable(struct
> intel_fbc *fbc)
>
> __intel_fbc_cleanup_cfb(fbc);
>
> + /* wa_18038517565 Enable DPFC clock gating after FBC disable
> */
> + if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> + fbc_compressor_clkgate_disable_wa(fbc, false);
> +
> fbc->state.plane = NULL;
> fbc->flip_pending = false;
> fbc->busy_bits = 0;
