Currently we are using value 50ms as timeout for waiting PSR to idle. Add
own define for this purpose.
Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index c2ab00fe2c20..172bc0c39968 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2982,6 +2982,14 @@ void intel_psr_post_plane_update(struct
intel_atomic_state *state,
}
}
+/*
+ * From bspec: Panel Self Refresh (BDW+)
+ * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
+ * exit training time + 1.5 ms of aux channel handshake. 50 ms is
+ * defensive enough to cover everything.
+ */
+#define PSR_IDLE_TIMEOUT_MS 50
+
static int
_psr2_ready_for_pipe_update_locked(const struct intel_crtc_state
*new_crtc_state)
{
@@ -2995,7 +3003,8 @@ _psr2_ready_for_pipe_update_locked(const struct
intel_crtc_state *new_crtc_state
*/
return intel_de_wait_for_clear(display,
EDP_PSR2_STATUS(display, cpu_transcoder),
- EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
+ EDP_PSR2_STATUS_STATE_DEEP_SLEEP,
+ PSR_IDLE_TIMEOUT_MS);
}
static int
@@ -3004,15 +3013,10 @@ _psr1_ready_for_pipe_update_locked(const struct
intel_crtc_state *new_crtc_state
struct intel_display *display = to_intel_display(new_crtc_state);
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
- /*
- * From bspec: Panel Self Refresh (BDW+)
- * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
- * exit training time + 1.5 ms of aux channel handshake. 50 ms is
- * defensive enough to cover everything.
- */
return intel_de_wait_for_clear(display,
psr_status_reg(display, cpu_transcoder),
- EDP_PSR_STATUS_STATE_MASK, 50);
+ EDP_PSR_STATUS_STATE_MASK,
+ PSR_IDLE_TIMEOUT_MS);
}
/**
--
2.43.0
