> -----Original Message-----
> From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of
> Chaitanya Kumar Borah
> Sent: Friday, August 22, 2025 5:55 AM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Chauhan, Shekhar <shekhar.chau...@intel.com>; Atwood, Matthew S
> <matthew.s.atw...@intel.com>; Sousa, Gustavo
> <gustavo.so...@intel.com>; Dugast, Francois <francois.dug...@intel.com>
> Subject: [PATCH] drm/xe/wcl: Extend L3bank mask workaround
>
> The commit 9ab440a9d042 ("drm/xe/ptl: L3bank mask is not available on the
> media GT") added a workaround to ignore the fuse register that L3 bank
> availability as it did not contain valid values. Same is true for WCL
> therefore
> extend the workaround to cover it.
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com>
I interpret from the WA and PTL description that we don't want to push any
value, not even 0s,
to userspace if the L3 mask is not available for media GT.
LGTM,
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhad...@intel.com>
> ---
> drivers/gpu/drm/xe/xe_wa_oob.rules | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules
> b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 8d0aabab6777..8bef2f567faf 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -48,7 +48,7 @@
> 16023588340 GRAPHICS_VERSION(2001),
> FUNC(xe_rtp_match_not_sriov_vf)
> 14019789679 GRAPHICS_VERSION(1255)
> GRAPHICS_VERSION_RANGE(1270, 2004)
> -no_media_l3 MEDIA_VERSION(3000)
> +no_media_l3 MEDIA_VERSION_RANGE(3000, 3002)
> 14022866841 GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
> MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
> 16021333562 GRAPHICS_VERSION_RANGE(1200, 1274)
> --
> 2.25.1
