On 9/18/2025 2:04 AM, Ville Syrjala wrote:
From: Ville Syrjälä <ville.syrj...@linux.intel.com> In order to pretend that ICL/TGL VRR hardware has a similar guardband as on ADL+ we'll need access to framestart_delay already during intel_vrr_get_config(). Hoist the framestart_delay to an earlier point to make that possible. Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
--- drivers/gpu/drm/i915/display/intel_display.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a743d1339550..c7d85fd38890 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3891,6 +3891,15 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_joiner_get_config(pipe_config); intel_dsc_get_config(pipe_config);+ if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {+ tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); + + pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; + } else { + /* no idea if this is correct */ + pipe_config->framestart_delay = 1; + } + if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || DISPLAY_VER(display) >= 11) intel_get_transcoder_timings(crtc, pipe_config); @@ -3942,15 +3951,6 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, pipe_config->pixel_multiplier = 1; }- if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {- tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); - - pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; - } else { - /* no idea if this is correct */ - pipe_config->framestart_delay = 1; - } - out: intel_display_power_put_all_in_set(display, &crtc->hw_readout_power_domains);
