From: Ville Syrjälä <ville.syrj...@linux.intel.com>
A bunch of claenup to the watermark latency setup on skl+, and
a few potential fixes for some edge cases.
v2: Repost the whole thing to help CI apply it
Ville Syrjälä (13):
drm/i915/dram: Also apply the 16Gb DIMM w/a for larger DRAM chips
drm/i915: Apply the 16Gb DIMM w/a only for the platforms that need it
drm/i915: Tweak the read latency fixup code
drm/i915: Don't pass the latency array to {skl,mtl}_read_wm_latency()
drm/i915: Move adjust_wm_latency() out from
{mtl,skl}_read_wm_latency()
drm/i915: Extract multiply_wm_latency() from skl_read_wm_latency()
drm/i915: Extract increase_wm_latency()
drm/i915: Use increase_wm_latency() for the 16Gb DIMM w/a
drm/i915: Extract sanitize_wm_latency()
drm/i915: Flatten sanitize_wm_latency() a bit
drm/i915: Make wm latencies monotonic
drm/i915: Print both the original and adjusted wm latencies
drm/i915: Make sure wm block/lines are non-decreasing
drivers/gpu/drm/i915/display/skl_watermark.c | 158 +++++++++++++------
drivers/gpu/drm/i915/soc/intel_dram.c | 10 +-
2 files changed, 116 insertions(+), 52 deletions(-)
--
2.49.1
