Until LNL, intel_dsb_wait_vblanks() waits for the undelayed vblank start.
However, from PTL onwards, it waits for the start of the safe window,
defined by the number of lines programmed in TRANS_SET_CONTEXT_LATENCY.
This change was introduced to move the SCL window out of the vblank region,
supporting modes with higher refresh rates and smaller vblanks.
As a result, on PTL+ platforms, the DSB wait for vblank completes exactly
SCL lines earlier than the undelayed vblank start. Since we use
intel_dsb_wait_vblanks() to time the send push operation, this causes
issues when SCL lines are non-zero.
So instruct the DSB to wait from (undelayed vblank start - SCL) to
(delayed vblank start - SCL) in the helper to wait for delayed vblank.
v2:
- Use helpers for safe window start/end. (Ville)
- Move the extra wait inside the helper to wait for delayed vblank. (Ville)
- Update the commit message.
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
3 files changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0584a9597327..e118ba4a0bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -815,6 +815,23 @@ void intel_dsb_chain(struct intel_atomic_state *state,
wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0);
}
+static
+void intel_dsb_wait_for_scl_start(struct intel_atomic_state *state,
+ struct intel_dsb *dsb)
+{
+ struct intel_crtc *crtc = dsb->crtc;
+ const struct intel_crtc_state *crtc_state =
+ intel_pre_commit_crtc_state(state, crtc);
+ int start, end;
+
+ if (!pre_commit_is_vrr_active(state, crtc))
+ return;
+
+ start = intel_vrr_safe_window_start(crtc_state);
+ end = intel_vrr_safe_window_end(crtc_state);
+ intel_dsb_wait_scanline_out(state, dsb, start, end);
+}
+
void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state,
struct intel_dsb *dsb)
{
@@ -824,6 +841,7 @@ void intel_dsb_wait_for_delayed_vblank(struct
intel_atomic_state *state,
int usecs = intel_scanlines_to_usecs(&crtc_state->hw.adjusted_mode,
dsb_vblank_delay(state, crtc));
+ intel_dsb_wait_for_scl_start(state, dsb);
intel_dsb_wait_usec(dsb, usecs);
}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 40e256bce3cb..8f851d3a3f44 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -800,3 +800,20 @@ void intel_vrr_get_config(struct intel_crtc_state
*crtc_state)
if (crtc_state->vrr.enable)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
+
+int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (DISPLAY_VER(display) >= 30)
+ return crtc_state->hw.adjusted_mode.crtc_vdisplay -
+ crtc_state->set_context_latency;
+
+ return crtc_state->hw.adjusted_mode.crtc_vdisplay;
+}
+
+int intel_vrr_safe_window_end(const struct intel_crtc_state *crtc_state)
+{
+ return intel_vrr_vmin_vblank_start(crtc_state) -
+ crtc_state->set_context_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index b72e90b4abe5..a304b6c41103 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -41,5 +41,7 @@ void intel_vrr_transcoder_enable(const struct
intel_crtc_state *crtc_state);
void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state);
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
+int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
+int intel_vrr_safe_window_end(const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_VRR_H__ */
--
2.45.2
