In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.
With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.
Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.
Introduce a helper to compute the minimal sufficient guardband.
v2: Use helpers for dsc/scaler prefill latencies. (Mitul)
Account for pkgc latency and take max of pkgc and sagv latencies.
v3: Use new helper for PSR2/Panel Replay latency.
v4: Avoid re-setting the Vmin/Flipline for optimized guardband.
v5:
- Refactor the function to make it as a helper which can be used to
update crtc_vblank_start and guardband can then be derived from it.
(Ville)
- Modify the subject and commit message for the same.
v6: Use intel_usecs_to_scanlines() instead of hand rolled stuff. (Ville)
Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com> (#v3)
---
drivers/gpu/drm/i915/display/intel_vrr.c | 117 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr.h | 2 +
2 files changed, 119 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4bc14b5e685f..a43e5ee2d3ac 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,18 @@
#include <drm/drm_print.h>
+#include "intel_alpm.h"
+#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dp.h"
+#include "intel_vdsc.h"
#include "intel_vrr.h"
#include "intel_vrr_regs.h"
+#include "skl_scaler.h"
+#include "skl_watermark.h"
#define FIXED_POINT_PRECISION 100
#define CMRR_PRECISION_TOLERANCE 10
@@ -839,3 +845,114 @@ int intel_vrr_vmin_safe_window_end(const struct
intel_crtc_state *crtc_state)
return intel_vrr_vmin_vblank_start(crtc_state) -
crtc_state->set_context_latency;
}
+
+static
+int scaler_prefill_latency(struct intel_crtc_state *crtc_state, int
linetime_us)
+{
+ int chroma_downscaling_factor =
skl_scaler_chroma_downscale_factor(crtc_state);
+ u64 hscale_k, vscale_k;
+ int cdclk_adjustment;
+ int num_scaler_users;
+
+ /*
+ * Assuming:
+ * Both scaler enabled.
+ * scaler 1 downscaling factor as 2 x 2 (Horiz x Vert)
+ * scaler 2 downscaling factor as 2 x 1 (Horiz x Vert)
+ * Cdclk Adjustment : 1
+ */
+ num_scaler_users = 2;
+ hscale_k = 2 * 1000;
+ vscale_k = 2 * 1000;
+ cdclk_adjustment = 1;
+
+ return skl_scaler_guardband_latency(num_scaler_users, hscale_k,
vscale_k,
+ chroma_downscaling_factor,
+ cdclk_adjustment,
+ linetime_us);
+}
+
+static
+int dsc_prefill_latency(struct intel_crtc_state *crtc_state, int linetime_us)
+{
+#define MAX_SCALERS 2
+ int chroma_downscaling_factor =
skl_scaler_chroma_downscale_factor(crtc_state);
+ u64 hscale_k[MAX_SCALERS], vscale_k[MAX_SCALERS];
+ int cdclk_adjustment;
+ int num_scaler_users;
+
+ /*
+ * Assuming:
+ * Both scaler enabled.
+ * scaler 1 downscaling factor as 2 x 2 (Horiz x Vert)
+ * scaler 2 downscaling factor as 2 x 1 (Horiz x Vert)
+ * Cdclk Adjustment : 1
+ */
+ num_scaler_users = MAX_SCALERS;
+ hscale_k[0] = 2 * 1000;
+ vscale_k[0] = 2 * 1000;
+ hscale_k[1] = 2 * 1000;
+ vscale_k[1] = 1 * 1000;
+
+ cdclk_adjustment = 1;
+
+ return intel_dsc_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+ chroma_downscaling_factor,
+ cdclk_adjustment,
+ linetime_us);
+}
+
+int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
+ struct intel_connector *connector)
+{
+ const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
+ struct intel_display *display = to_intel_display(crtc_state);
+ int dsc_prefill_time = 0;
+ int psr2_pr_latency = 0;
+ int scaler_prefill_time;
+ int wm0_prefill_time;
+ int pkgc_max_latency;
+ int sagv_latency;
+ int sdp_latency = 0;
+ int guardband_us;
+ int linetime_us;
+ int guardband;
+ int pm_delay;
+
+ linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+ adjusted_mode->crtc_clock);
+
+ pkgc_max_latency = skl_watermark_max_latency(display, 1);
+ sagv_latency = display->sagv.block_time_us;
+
+ /* Assuming max wm0 lines = 4 */
+ wm0_prefill_time = 4 * linetime_us + 20;
+
+ scaler_prefill_time = scaler_prefill_latency(crtc_state, linetime_us);
+
+ if (crtc_state->dsc.compression_enable)
+ dsc_prefill_time = dsc_prefill_latency(crtc_state, linetime_us);
+
+ pm_delay = crtc_state->framestart_delay +
+ max(sagv_latency, pkgc_max_latency) +
+ wm0_prefill_time +
+ scaler_prefill_time +
+ dsc_prefill_time;
+
+ switch (connector->base.connector_type) {
+ case DRM_MODE_CONNECTOR_eDP:
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ psr2_pr_latency =
intel_alpm_compute_max_link_wake_latency(crtc_state, true);
+ sdp_latency = intel_dp_compute_sdp_latency(crtc_state, true);
+ break;
+ default:
+ break;
+ }
+
+ guardband_us = max(sdp_latency, psr2_pr_latency);
+ guardband_us = max(guardband_us, pm_delay);
+
+ guardband = intel_usecs_to_scanlines(adjusted_mode, guardband_us);
+
+ return guardband;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h
b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7317f8730089..d332e5a0a1c1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,5 +42,7 @@ void intel_vrr_set_fixed_rr_timings(const struct
intel_crtc_state *crtc_state);
bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
+int intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
+ struct intel_connector *connector);
#endif /* __INTEL_VRR_H__ */
--
2.45.2
