This patchset fixes the DP/HDMI mode programming for C20 PHY PLLs. While at it, it also adds the missing port clock HW readout for C10 PHY PLLs. These patches were originally part of the RFC PLL rework patch series [1], now resent separately since they include a fix, which as such should be tested/merged separately.
[1] https://lore.kernel.org/all/[email protected] Imre Deak (7): drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE field macros drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag macro drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL flag macro drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming drm/i915/display: Add missing clock to C10 PHY state compute/HW readout drivers/gpu/drm/i915/display/intel_cx0_phy.c | 43 ++++++++++++------- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 10 +++-- .../drm/i915/display/intel_snps_hdmi_pll.c | 2 + 3 files changed, 36 insertions(+), 19 deletions(-) -- 2.34.1
