From: Ville Syrjälä <[email protected]> Adjust intel_cdclk_prefill_adjustment() to give out a potentially more optimal value, purely based on the final minimum CDCLK (also considering planes/pfit/etc.) for the current pipe. We can't actually check against the current CDCLK frequency as that might be much higher due to some other pipe, and said other pipe might later reduce the CDCLK below what the current pipe would find acceptable (given which WM levels are enabled). Ie. we don't consider any global constraints (other pipes, dbuf bandwidth, etc) on the mimimum CDCLK frequency here.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index e92e7fd9fd13..838834c49a90 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -4092,8 +4092,21 @@ static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state) { - /* FIXME use the actual min_cdclk for the pipe here */ - return intel_cdclk_prefill_adjustment_worst(crtc_state); + int clock = crtc_state->hw.pipe_mode.crtc_clock; + int min_cdclk; + + /* + * Only consider the current pipe's minimum cdclk here as a safe + * lower bound. This must *not* be based on the actual/logical cdclk + * frequency here as that may get reduced later due to eg. a modeset + * on a different pipe, and that would completely invalidate the + * guardband length checks we did on this pipe previously. That + * could lead to prefill exceeding the guardband which would result + * in underruns. + */ + min_cdclk = crtc_state->min_cdclk; + + return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk); } unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state) -- 2.49.1
