Quoting Gustavo Sousa (2025-11-07 21:05:33-03:00) >This series adds initial support for Xe3p_LPD, Intel's display >architecture with IP version 35. > >This series contains basic enabling patches and does not provide >complete support for the display IP yet. More involved features, like >the new PHY implementation and ALPM are implemented as separate patch >series. > >Signed-off-by: Gustavo Sousa <[email protected]> >--- >Changes in v4: >- Skipped patches from v3 that were already applied. >- Dropped patch "drm/i915/xe3p_lpd: Enable system caching for FBC" with > the expectation that its next version will be sent as a standalone > patch. >- Link to v3: >https://patch.msgid.link/[email protected]
I decided to post v4 even though there is still some ongoing discussion for "drm/i915/wm: Do not make latency values monotonic on Xe3 onward" in v3. The reason is that I will soon become unavailable for a few days and wanted to keep the series up-to-date with what I have locally. -- Gustavo Sousa > >Changes in v3: >- Reshuffled patches so that most of the ones already containing a r-b > are placed at the start. >- Dropped "drm/i915/xe3p_lpd: Wait for AUX channel power status", as a > similar patch was already applied from a patch series dedicated to LT > PHY > > (https://lore.kernel.org/all/[email protected]/). >- Dropped patches related to UINT16 plane formats, as they were > incomplete and were not specific to Xe3p_LPD. >- Dropped FBC related patches, as Vinod is handling them as a separated > series > > (https://lore.kernel.org/intel-gfx/[email protected]/) >- Dropped "drm/i915/xe3p_lpd: PSR SU minimum lines is 4", since that > change is not valid according to Bspec. >- Incorporated review feedback on the other patches. Please check the > changelog in the individual patches for details. >- Link to v2: >https://lore.kernel.org/r/[email protected] > >Changes in v2: >- Incorporated review feedback. Please check the changelog in the > patches for details. >- Link to v1: >https://lore.kernel.org/r/[email protected] > >--- >Gustavo Sousa (10): > drm/i915/wm: Do not make latency values monotonic on Xe3 onward > drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc > drm/i915/power: Use intel_encoder_is_tc() > drm/i915/display: Handle dedicated external ports in > intel_encoder_is_tc() > drm/i915/fbc: Add intel_fbc_id_for_pipe() > drm/i915/xe3p_lpd: Handle underrun debug bits > drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation > drm/i915/display: Use platform check in HAS_LT_PHY() > drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h > drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power > >Sai Teja Pottumuttu (1): > drm/i915/nvls: Add NVL-S display support > > drivers/gpu/drm/i915/display/intel_bios.c | 54 +++++++- > drivers/gpu/drm/i915/display/intel_bios.h | 2 + > drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++ > drivers/gpu/drm/i915/display/intel_display.c | 19 ++- > .../gpu/drm/i915/display/intel_display_device.c | 5 + > .../gpu/drm/i915/display/intel_display_device.h | 6 +- > .../drm/i915/display/intel_display_power_well.c | 42 +++--- > drivers/gpu/drm/i915/display/intel_display_regs.h | 36 ++++- > drivers/gpu/drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_fbc.c | 5 + > drivers/gpu/drm/i915/display/intel_fbc.h | 2 + > drivers/gpu/drm/i915/display/intel_fbc_regs.h | 2 + > drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 128 +++++++++++++++++ > drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 - > drivers/gpu/drm/i915/display/intel_tc.c | 151 ++++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 +- > drivers/gpu/drm/i915/display/skl_watermark.c | 17 ++- > 18 files changed, 462 insertions(+), 33 deletions(-) >--- >base-commit: 2bc418aa7efaae562e49d84e8b28f799cf624745 >change-id: 20251014-xe3p_lpd-basic-enabling-eb4424698b44 > >Best regards, >-- >Gustavo Sousa <[email protected]> >
