[RFC 6/8] drm/i915/cmtg: set transcoder mn for cmtg

[Animesh Manna]

Program CMTG link M/N.

Signed-off-by: Animesh Manna <animesh.ma...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h |  3 +++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c 
b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 6086ba4d764f..0a804554f16d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -247,6 +247,16 @@ static void intel_cmtg_set_timings(const struct 
intel_crtc_state *crtc_state)
        }
 }
 
+static void intel_cpu_cmtg_transcoder_set_m_n(const struct intel_crtc_state 
*crtc_state)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+       const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+       intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
+       intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
+}
+
 void intel_cmtg_enable(const struct intel_crtc_state *crtc_state)
 {
        struct intel_display *display = to_intel_display(crtc_state);
@@ -261,4 +271,7 @@ void intel_cmtg_enable(const struct intel_crtc_state 
*crtc_state)
        /* Program context latency */
        intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
                       intel_de_read(display, 
TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder)));
+
+       /* Program CMTG MN */
+       intel_cpu_cmtg_transcoder_set_m_n(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h 
b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 406b5eb385a5..1bbdb66ee587 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -33,6 +33,9 @@ enum cmtg {
 #define TRANS_VBLANK_CMTG(id)          _MMIO(0x6F010 + (id) * 0x100)
 #define TRANS_VSYNC_CMTG(id)           _MMIO(0x6F014 + (id) * 0x100)
 
+#define TRANS_LINKM1_CMTG(id)          _MMIO(0x6F040 + (id) * 0x100)
+#define TRANS_LINKN1_CMTG(id)          _MMIO(0x6F044 + (id) * 0x100)
+
 #define TRANS_SET_CTX_LATENCY_CMTG(id) _MMIO(0x6F07C + (id) * 0x100)
 
 #define TRANS_VRR_CTL_CMTG(id)         _MMIO(0x6F420 + (id) * 0x100)
-- 
2.29.0