On Wed, Nov 19, 2025 at 11:59:49AM +0000, Kahola, Mika wrote: > > -----Original Message----- > > From: Kahola, Mika <[email protected]> > > Sent: Monday, 17 November 2025 12.46 > > To: [email protected]; [email protected] > > Cc: Kahola, Mika <[email protected]> > > Subject: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll > > framework > > > > This is v2 of [1], with the following changes > > > > - commit message updates > > - Use of BUILD_BUGON() wherever possible instead of WARN_ON() > > > > [1] > > https://lore.kernel.org/intel-gfx/[email protected]/ > > This pll refactoring series is now merged. Thank you, Suraj, for taking time > and effort to review this big series.
It looks like Xe.CI.Full reported some BMG driver load warnings that may have been overlooked: https://lore.kernel.org/all/176338618409.2038.14088991238815121493@a3b018990fe9/ Now that this has been merged, those same driver load issues are starting to show up on premerge CI for other series. Can you take a look? Matt > > -Mika- > > > > > Imre Deak (15): > > drm/i915/cx0: Factor out C10 msgbus access start/end helpers > > drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag > > drm/i915/cx0: Sanitize calculating C20 PLL state from tables > > drm/i915/cx0: Track the C20 PHY VDR state in the PLL state > > drm/i915/cx0: Move definition of Cx0 PHY functions earlier > > drm/i915/cx0: Add macro to get DDI port width from a register value > > drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state > > drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup > > drm/i915/cx0: Read out the Cx0 PHY SSC enabled state > > drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state > > drm/i915/cx0: Determine Cx0 PLL port clock from PLL state > > drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout > > drm/i915/cx0: Print additional Cx0 PLL HW state > > drm/i915/cx0: PLL verify debug state print > > drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks > > > > Mika Kahola (17): > > drm/i915/cx0: Rename TBT functions to be ICL specific > > drm/i915/cx0: Remove state verification > > drm/i915/cx0: Add PLL information for MTL+ > > drm/i915/cx0: Update C10/C20 state calculation > > drm/i915/cx0: Compute plls for MTL+ platform > > drm/i915/cx0: Add MTL+ .get_dplls hook > > drm/i915/cx0: Add MTL+ .put_dplls hook > > drm/i915/cx0: Add MTL+ .update_active_dpll hook > > drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook > > drm/i915/cx0: Add MTL+ .dump_hw_state hook > > drm/i915/cx0: Add .compare_hw_state hook > > drm/i915/cx0: Add MTL+ .get_hw_state hook > > drm/i915/cx0: Add MTL+ .get_freq hook > > drm/i915/cx0: Add MTL+ .crtc_get_dpll hook > > drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI > > drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs > > drm/i915/cx0: Enable dpll framework for MTL+ > > > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 870 ++++++++++-------- > > drivers/gpu/drm/i915/display/intel_cx0_phy.h | > > 29 +- > > drivers/gpu/drm/i915/display/intel_ddi.c | 87 +- > > drivers/gpu/drm/i915/display/intel_display.c | 30 - > > .../gpu/drm/i915/display/intel_display_regs.h | 7 +- > > drivers/gpu/drm/i915/display/intel_dpll.c | 24 +- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 315 ++++++- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 7 + > > drivers/gpu/drm/i915/display/intel_lt_phy.c | 4 +- > > .../drm/i915/display/intel_modeset_verify.c | 1 - > > 10 files changed, 893 insertions(+), 481 deletions(-) > > > > -- > > 2.34.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
