On 11/20/25 10:18, Jason Gunthorpe wrote:
On Wed, Nov 19, 2025 at 11:56:16PM +0000, Tian, Kevin wrote:
So we should be using dmar->width to constrain the first stage and
expect that mgaw is less than dmar->width ?
dmar->width is the host address width, i.e. for OA. so it's irrelevant
to the input iova here.
Oh that makes sense!
In that case we should probably pedantically have:
cfg.common.hw_max_oasz_lg2 = dmar->width;
?
However we get dmar into that function?
I will consider this and come up with a follow-up patch if needed.
"
3.6 First-Stage Translation
First-stage translation restricts the input-address to a canonical address
(i.e., address bits 63:N have the same value as address bit [N-1], where
N is 48 bits with 4-level paging and 57 bits with 5-level paging). Requests
subject to first-stage translation by remapping hardware are subject to
canonical address checking as a pre-condition for first-stage translation,
and a violation is treated as a translation-fault.
Software using first-stage translation structures to translate an IO Virtual
Address (IOVA) must use canonical addresses. Additionally, software
must limit addresses to less than the minimum of MGAW and the lower
canonical address width implied by FSPM (i.e., 47-bit when FSPM is 4-level
and 56-bit when FSPM is 5-level)
"
That seems very clear, indeed. OK! Easy to fix then! Balou can you
take it? I think something like this?
Yes, sure. I will make it a formal patch and post it for further testing
after some sanity checks.
Thanks,
baolu
