On Fri, 2025-11-28 at 18:20 +0200, Imre Deak wrote: > Use intel_dp_effective_data_rate() to calculate the required link BW > for > compressed streams on non-UHBR DP-SST links. This ensures that the BW > is > calculated the same way for all DP output types and DSC/non-DSC > modes, > during mode validation as well as during state computation. > > This approach also allows for accounting with BW overhead due to DSC, > FEC being enabled on a link. Acounting for these will be added by > follow-up changes. > > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++-------- > -- > 1 file changed, 16 insertions(+), 11 deletions(-) >
Reviewed-by: Vinod Govindapillai <[email protected]> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index aa55a81a9a9bf..4044bdbceaef5 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2025,15 +2025,19 @@ static bool > intel_dp_dsc_supports_format(const struct intel_connector *connector > return drm_dp_dsc_sink_supports_format(connector- > >dp.dsc_dpcd, sink_dsc_format); > } > > -static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 > link_clock, > - u32 lane_count, u32 > mode_clock, > - enum intel_output_format > output_format, > - int timeslots) > +static bool is_bw_sufficient_for_dsc_config(struct intel_dp > *intel_dp, > + int link_clock, int > lane_count, > + int mode_clock, int > mode_hdisplay, > + int dsc_slice_count, int > link_bpp_x16, > + unsigned long > bw_overhead_flags) > { > - u32 available_bw, required_bw; > + int available_bw; > + int required_bw; > > - available_bw = (link_clock * lane_count * timeslots * 16) / > 8; > - required_bw = dsc_bpp_x16 * > (intel_dp_mode_to_fec_clock(mode_clock)); > + available_bw = intel_dp_max_link_data_rate(intel_dp, > link_clock, lane_count); > + required_bw = intel_dp_link_required(link_clock, lane_count, > + mode_clock, > mode_hdisplay, > + link_bpp_x16, > bw_overhead_flags); > > return available_bw >= required_bw; > } > @@ -2081,11 +2085,12 @@ static int dsc_compute_link_config(struct > intel_dp *intel_dp, > if (ret) > continue; > } else { > - if > (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, > - > lane_count, > + if > (!is_bw_sufficient_for_dsc_config(intel_dp, > + > link_rate, lane_count, > > adjusted_mode->crtc_clock, > - > pipe_config->output_format, > - > timeslots)) > + > adjusted_mode->hdisplay, > + > pipe_config->dsc.slice_count, > + > dsc_bpp_x16, 0)) > continue; > } >
