On Thu, 2025-11-27 at 19:49 +0200, Imre Deak wrote: > Make sure that state computation fails if the minimum/maximum link BPP > values got invalid as a result of limiting both of these values > separately to the corresponding source/sink capability limits. > > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 3111758578d6c..545d872a30403 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2654,7 +2654,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp > *intel_dp, > limits->link.max_bpp_x16 = max_link_bpp_x16; > > drm_dbg_kms(display->drm, > - "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d > kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT > "\n", > + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d > kHz DSC %s max lanes %d max rate %d max pipe_bpp %d min link_bpp " FXP_Q4_FMT > " max link_bpp " FXP_Q4_FMT "\n", > encoder->base.base.id, encoder->base.name, > crtc->base.base.id, crtc->base.name, > adjusted_mode->crtc_clock, > @@ -2662,8 +2662,13 @@ intel_dp_compute_config_link_bpp_limits(struct > intel_dp *intel_dp, > limits->max_lane_count, > limits->max_rate, > limits->pipe.max_bpp, > + FXP_Q4_ARGS(limits->link.min_bpp_x16), > FXP_Q4_ARGS(limits->link.max_bpp_x16)); > > + if (limits->link.min_bpp_x16 <= 0 || > + limits->link.min_bpp_x16 > limits->link.max_bpp_x16) > + return false; > + > return true; > } >
Reviewed-by: Luca Coelho <[email protected]> -- Cheers, Luca.
