CX0 PHY currently has two issues which cause a hang when we try to suspend resume machine with a delay of 15mins and 1+ hour. This happens due to two reasons: 1) We do not follow the Enablement sequence where we need to enable our clock after PPS Enablement cycle 2) We do not make sure response ready and error bit are cleared in P2M_MSGBUS_STATUS before writing the transaction pending bit. This series aims to solve this.
Signed-off-by: Suraj Kandpal <[email protected]> Mika Kahola (1): drm/i915/pps: Enable panel power earlier Suraj Kandpal (2): drm/i915/cx0: Clear response ready & error bit drm/i915/cx0: Rename intel_clear_response_ready flag drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++++----- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 ++-- drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++ drivers/gpu/drm/i915/display/intel_lt_phy.c | 2 +- 5 files changed, 21 insertions(+), 10 deletions(-) -- 2.34.1
