"Bhadane, Dnyaneshwar" <[email protected]> writes:
>> -----Original Message----- >> From: Intel-xe <[email protected]> On Behalf Of Gustavo >> Sousa >> Sent: Tuesday, February 3, 2026 3:13 AM >> To: [email protected]; [email protected] >> Cc: Sousa, Gustavo <[email protected]>; Roper, Matthew D >> <[email protected]> >> Subject: [PATCH 05/16] drm/xe/xe3p_lpg: Add MCR steering >> >> From: Matt Roper <[email protected]> >> >> Xe3p_LPG has nearly identical steering to Xe2 and Xe3. The only DSS/XeCore >> change from those IPs is an additional range from 0xDE00-0xDE7F that was >> previously reserved, so we can simply grow one of the existing ranges in the >> Xe2 >> table to include it. Similarly, the "instance0" table is also almost >> identical, but >> gains one additional PSMI range and requires a separate table. >> >> Bspec: 75242 >> Signed-off-by: Matt Roper <[email protected]> >> Signed-off-by: Gustavo Sousa <[email protected]> >> --- >> drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c >> index 7c1fe9ac120d..b112e551fc79 100644 >> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c >> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c >> @@ -201,7 +201,7 @@ static const struct xe_mmio_range >> xe2lpg_dss_steering_table[] = { >> { 0x009680, 0x0096FF }, /* DSS */ >> { 0x00D800, 0x00D87F }, /* SLICE */ >> { 0x00DC00, 0x00DCFF }, /* SLICE */ >> - { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */ >> + { 0x00DE00, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */ >> { 0x00E980, 0x00E9FF }, /* SLICE */ >> { 0x013000, 0x0133FF }, /* DSS (0x13000-0x131FF), SLICE >> (0x13200- >> 0x133FF) */ >> {}, >> @@ -280,6 +280,19 @@ static const struct xe_mmio_range >> xe3p_xpc_instance0_steering_table[] = { >> {}, >> }; >> >> +static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = { >> + { 0x004000, 0x004AFF }, /* GAM, rsvd, GAMWKR */ >> + { 0x008700, 0x00887F }, /* NODE */ >> + { 0x00B000, 0x00B3FF }, /* NODE, L3BANK */ >> + { 0x00B500, 0x00B6FF }, /* PSMI */ > Hi, > Could we extend the range till 0x00BEFF ? >> + { 0x00C800, 0x00CFFF }, /* GAM */ >> + { 0x00D880, 0x00D8FF }, /* NODE */ >> + { 0x00DD00, 0x00DDFF }, /* MEMPIPE */ > Same as we did here extend till reserved. We usually only include a reserved range if the range is preceeded and followed by MCR ranges of the same steering group. This doesn't seem to be the case here. -- Gustavo Sousa
