> Subject: Re: [PATCH] drm/i915/ltphy: Return true for TBT scenario during > lt_phy_state compare > > On Tue, Feb 03, 2026 at 10:40:33AM +0200, Kandpal, Suraj wrote: > > > Subject: Re: [PATCH] drm/i915/ltphy: Return true for TBT scenario > > > during lt_phy_state compare > > > > > > On Tue, Feb 03, 2026 at 08:11:41AM +0530, Suraj Kandpal wrote: > > > > TBT PHY is enablement/disablement is handled by its own TBT module. > > > > We do not play a big part in it's state management that being take > > > > care by it's own TBT modeule. With that in mind comparing the > > > > state would be wrong since we really don't touch it. > > > > Simple return true when we are in tbt mode. > > > > > > > > Signed-off-by: Suraj Kandpal <[email protected]> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_lt_phy.c | 3 +++ > > > > 1 file changed, 3 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c > > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c > > > > index 04f63bdd0b87..27ad8407606b 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > > > > @@ -2158,6 +2158,9 @@ bool > > > > intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state > *a, > > > > const struct intel_lt_phy_pll_state > > > > *b) { > > > > + if (a->tbt_mode || b->tbt_mode) > > > > + return true; > > > > > > It is a relevant state whether the PHY is in TBT mode or in a > > > non-TBT mode, even if the PHY is programmed by the TBT HW block in > > > TBT mode. So it's not ok to ignore a difference in this state. > > > Please provide the actual context for why the change was added. > > > > Bspec : 74492 > > > > We do not write the PLL registers when it comes to TBT Mode that is > > done by the TBT dock. Since the VDR register are shadow registers our > > shadow registers will never have those values. Which Means we will > > always have a state mismatch. > > Reading out the HW state of the actual PLL dividers and configuration is not > read out in TBT mode for the above reason but the verification is skipped in > TBT mode for another reason: > > The PHY/PLL TypeC mode (TBT, DP-alt) can change after the PLL state was > computed for a modeset, so the state verification after the modeset sequence > would indicate a mismatch in case the mode changed from DP-alt to TBT, or > from TBT to DP-alt mode. To avoid such a mismatch error the verification is > skipped if the mode for either the read-out or the computed state is TBT > (where that TBT PLL state doesn't reflect anyway the PLL's actual HW state). > > Could you please amend the commit long along the above lines as a rationale > for the change?
Sure will amend and send the next revision Regards, Suraj Kandpal > > > This has always been the case since SNPS PHY. Check > > intel_cx0pll_compare_hw_state int intel_cx0_phy.c too > > > > Regards, > > Suraj Kandpal > > > > > > > > > + > > > > /* > > > > * With LT PHY values other than VDR0_CONFIG and VDR2_CONFIG are > > > > * unreliable. They cannot always be read back since internally > > > > -- > > > > 2.34.1 > > > >
