We can just create a ->post_disable hook to shovel all the fdi/pch specific code into it - it's all only used by the crt encoder anyway.
Signed-off-by: Daniel Vetter <[email protected]> --- drivers/gpu/drm/i915/intel_crt.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 18 ------------------ 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 0e109325cbcb..208f54f28d08 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -355,6 +355,31 @@ static void hsw_crt_disable(struct intel_encoder *encoder) TRANSCODER_A, false); } +static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) +{ + u32 val; + + val = I915_READ(LPT_TRANSCONF); + val &= ~TRANS_ENABLE; + I915_WRITE(LPT_TRANSCONF, val); + /* wait for PCH transcoder off, transcoder state */ + if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) + DRM_ERROR("Failed to disable PCH transcoder\n"); + + /* Workaround: clear timing override bit. */ + val = I915_READ(_TRANSA_CHICKEN2); + val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; + I915_WRITE(_TRANSA_CHICKEN2, val); +} + +static void hsw_crt_post_disable(struct intel_encoder *encoder) +{ + struct drm_device *dev = encoder->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + lpt_disable_pch_transcoder(dev_priv); +} + static void intel_enable_crt(struct intel_encoder *encoder) { struct intel_crt *crt = intel_encoder_to_crt(encoder); @@ -1165,6 +1190,7 @@ void intel_crt_init(struct drm_device *dev) crt->base.pre_enable = hsw_crt_pre_enable; crt->base.enable = hsw_crt_enable; crt->base.disable = hsw_crt_disable; + crt->base.post_disable = hsw_crt_post_disable; } else { crt->base.get_config = intel_crt_get_config; crt->base.get_hw_state = intel_crt_get_hw_state; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 84f5cbd3863c..0e2c9f242b4d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1718,23 +1718,6 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, } } -static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) -{ - u32 val; - - val = I915_READ(LPT_TRANSCONF); - val &= ~TRANS_ENABLE; - I915_WRITE(LPT_TRANSCONF, val); - /* wait for PCH transcoder off, transcoder state */ - if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) - DRM_ERROR("Failed to disable PCH transcoder\n"); - - /* Workaround: clear timing override bit. */ - val = I915_READ(_TRANSA_CHICKEN2); - val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(_TRANSA_CHICKEN2, val); -} - /** * intel_enable_pipe - enable a pipe, asserting requirements * @crtc: crtc responsible for the pipe @@ -3857,7 +3840,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) encoder->post_disable(encoder); if (intel_crtc->config.has_pch_encoder) { - lpt_disable_pch_transcoder(dev_priv); intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); intel_ddi_fdi_disable(crtc); } -- 1.8.1.4 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
