> Subject: [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os
* SoC & * OS > turnaround time Nit: This can be just drm/i915/cx0: You can keep cx0_phy_regs if you like but you need to drop the display > > The port refclk enable timeout and the soc ready timeout value mentioned in * SoC > the spec is the PHY timings and doesn't include the turnaround time from the > SoC or OS. So add an overhead timeout value on top of the recommended > timeouts from the PHY spec. > We can perhaps mention something like the timeout is increased based on stress testing Where we observed the move PHY stability With the above fixed, Reviewed-by: Suraj Kandpal <[email protected]> > Signed-off-by: Arun R Murthy <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > index > 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714 > a2bd2d6612cbbd4698 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h > @@ -78,10 +78,10 @@ > #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 > #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 > #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 > -#define XELPDP_PORT_RESET_START_TIMEOUT_US 5 > +#define XELPDP_PORT_RESET_START_TIMEOUT_US 10 > #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS > 2 > #define XELPDP_PORT_RESET_END_TIMEOUT_MS 15 > -#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1 > +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10 > > #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004 > #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104 > > -- > 2.25.1
