On top the timeouts mentioned in the spec which includes only the PHY timeouts include the SoC and the OS turnaround time. The overhead value is based on the stress test results with multiple available panels.
Signed-off-by: Arun R Murthy <[email protected]> Reviewed-by: Suraj Kandpal <[email protected]> --- drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h index 37e46fb9abde4156ebd7ad1eb6cbbc12e7026b23..ff6d7829dbb9c50b2001d079b435b894faf9659e 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h @@ -6,12 +6,12 @@ #ifndef __INTEL_LT_PHY_REGS_H__ #define __INTEL_LT_PHY_REGS_H__ -#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500 +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500 #define XE3PLPD_MACCLK_TURNON_LATENCY_MS 2 -#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1 +#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 10 #define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS 1 -#define XE3PLPD_RESET_START_LATENCY_US 10 -#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 4 +#define XE3PLPD_RESET_START_LATENCY_US 10 +#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 10 #define XE3PLPD_RESET_END_LATENCY_MS 2 /* LT Phy MAC Register */ -- 2.25.1
