> Subject: [PATCH 12/19] drm/i915/lt_phy: Add xe3plpd .get_freq hook
>
> Add .get_freq function hook to support dpll framework for xe3plpd platform.
>
> Signed-off-by: Mika Kahola <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_dpll.c | 5 -----
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
> 2 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 147baa777856..88f11cb8c5e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1219,17 +1219,12 @@ static int xe3plpd_crtc_compute_clock(struct
> intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder =
> intel_get_crtc_new_encoder(state, crtc_state);
> - struct intel_display *display = to_intel_display(encoder);
> int ret;
>
> ret = intel_lt_phy_pll_calc_state(crtc_state, encoder, &crtc_state-
> >dpll_hw_state);
> if (ret)
> return ret;
>
> - /* TODO: Do the readback via intel_compute_shared_dplls() */
> - crtc_state->port_clock =
> - intel_lt_phy_calc_port_clock(display, &crtc_state-
> >dpll_hw_state.ltpll);
> -
Do not remove this code till end of series where your whole framework is ready.
This introduces a bug interim.
Intel_crtc_dotclock uses the calculated port_clock.
Moreover calc_state is only called to calculate port_clock
Regards,
Suraj Kandpal
> crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6502916793f5..412582e29ca6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4583,8 +4583,21 @@ static bool xe3plpd_pll_get_hw_state(struct
> intel_display *display,
> return intel_lt_phy_pll_readout_hw_state(encoder, &dpll_hw_state-
> >ltpll); }
>
> +static int xe3plpd_pll_get_freq(struct intel_display *display,
> + const struct intel_dpll *pll,
> + const struct intel_dpll_hw_state
> *dpll_hw_state) {
> + struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> + if (drm_WARN_ON(display->drm, !encoder))
> + return -EINVAL;
> +
> + return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll); }
> +
> static const struct intel_dpll_funcs xe3plpd_pll_funcs = {
> .get_hw_state = xe3plpd_pll_get_hw_state,
> + .get_freq = xe3plpd_pll_get_freq,
> };
>
> static const struct dpll_info xe3plpd_plls[] = {
> --
> 2.43.0
