Re: [PATCH v3 4/4] drm/i915/psr: Write DSC parameters on Selective Update in ET mode

[Nautiyal, Ankit K]

On 3/4/2026 5:00 PM, Jouni Högander wrote:
There are slice row per frame and pic height parameters in DSC that needs
to be configured on every Selective Update in Early Transport mode. Use
helper provided by DSC code to configure these on Selective Update when in
Early Transport mode. Also fill crtc_state->psr2_su_area with full frame
area on full frame update for DSC calculation.

v2: move psr2_su_area under skip_sel_fetch_set_loop label

Bspec: 68927, 71709
Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
Cc: <sta...@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>

Makes sense to, make the su area full at the end, if full_frame update 
is needed.

Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>

---
  drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++++
  1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index 7b197e84e77d..cb3df2611515 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2618,6 +2618,12 @@ void intel_psr2_program_trans_man_trk_ctl(struct 
intel_dsb *dsb,
  
  	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
                           crtc_state->pipe_srcsz_early_tpt);
+
+       if (!crtc_state->dsc.compression_enable)
+               return;
+
+       intel_dsc_su_et_parameters_configure(dsb, encoder, crtc_state,
+                                            
drm_rect_height(&crtc_state->psr2_su_area));
  }
  
  static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -3039,6 +3045,10 @@ int intel_psr2_sel_fetch_update(struct 
intel_atomic_state *state,
        }
  
  skip_sel_fetch_set_loop:
+       if (full_update)
+               clip_area_update(&crtc_state->psr2_su_area, 
&crtc_state->pipe_src,
+                                &crtc_state->pipe_src);
+
        psr2_man_trk_ctl_calc(crtc_state, full_update);
        crtc_state->pipe_srcsz_early_tpt =
                psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);