As per DP specification,
The DP Source device may optionally enable PR optimization
with DP tunneling. The device shall query the Tunneling Bridge’s
PR tunneling optimization capability by way of the
Panel_Replay_Tunneling_Optimization_Support bit in the
DP_TUNNELING_CAPABILITIES register (DPCD E000Dh[6]), and then enable PR
only when the Tunneling Bridge is capable.
Therefore, do not enable Panel Replay for DP tunneling when optimization
support is not available.
Suggested-by: Jouni Högander <[email protected]>
Signed-off-by: Animesh Manna <[email protected]>
---
drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 27ba96ede8e2..a7818a556076 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1802,6 +1802,13 @@ static bool _panel_replay_compute_config(struct
intel_crtc_state *crtc_state,
crtc_state->link_off_after_as_sdp_when_pr_active =
compute_link_off_after_as_sdp_when_pr_active(connector);
crtc_state->disable_as_sdp_when_pr_active =
compute_disable_as_sdp_when_pr_active(connector);
+ if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp) &&
+ !connector->dp.panel_replay_caps.optimization_support) {
+ drm_dbg_kms(display->drm,
+ "Panel Replay is disabled as DP tunelling enabled
without optimization\n");
+ return false;
+ }
+
if (!intel_dp_is_edp(intel_dp))
return true;
--
2.29.0
