Add the fixed-function CSC block to color pipeline in SDR planes as a DRM_COLOROP_CSC_FF colorop.
Signed-off-by: Chaitanya Kumar Borah <[email protected]> --- .../drm/i915/display/intel_color_pipeline.c | 22 ++++++++++++++++++- .../drm/i915/display/intel_display_limits.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c index 6cf8080ee800..f368a896d2fc 100644 --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c @@ -43,6 +43,16 @@ static const enum intel_color_block hdr_plane_pipeline[] = { INTEL_PLANE_CB_POST_CSC_LUT, }; +static const enum intel_color_block sdr_plane_pipeline[] = { + INTEL_PLANE_CB_CSC_FF, +}; + +static const u64 intel_plane_supported_csc_ff = + BIT(DRM_COLOROP_CSC_FF_YUV601_RGB601) | + BIT(DRM_COLOROP_CSC_FF_YUV709_RGB709) | + BIT(DRM_COLOROP_CSC_FF_YUV2020_RGB2020) | + BIT(DRM_COLOROP_CSC_FF_RGB709_RGB2020); + static bool plane_has_3dlut(struct intel_display *display, enum pipe pipe, struct drm_plane *plane) { @@ -92,6 +102,12 @@ struct intel_colorop *intel_color_pipeline_plane_add_colorop(struct drm_plane *p DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, DRM_COLOROP_FLAG_ALLOW_BYPASS); break; + case INTEL_PLANE_CB_CSC_FF: + ret = drm_plane_colorop_csc_ff_init(dev, &colorop->base, plane, + &intel_colorop_funcs, + intel_plane_supported_csc_ff, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + break; default: drm_err(plane->dev, "Invalid colorop id [%d]", id); ret = -EINVAL; @@ -122,13 +138,17 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en int pipeline_len; int ret = 0; int i; + bool is_hdr = icl_is_hdr_plane(display, to_intel_plane(plane)->id); if (plane_has_3dlut(display, pipe, plane)) { pipeline = xe3plpd_primary_plane_pipeline; pipeline_len = ARRAY_SIZE(xe3plpd_primary_plane_pipeline); - } else { + } else if (is_hdr) { pipeline = hdr_plane_pipeline; pipeline_len = ARRAY_SIZE(hdr_plane_pipeline); + } else { + pipeline = sdr_plane_pipeline; + pipeline_len = ARRAY_SIZE(sdr_plane_pipeline); } for (i = 0; i < pipeline_len; i++) { diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h index 453f7b720815..f4aad54472ce 100644 --- a/drivers/gpu/drm/i915/display/intel_display_limits.h +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h @@ -167,6 +167,7 @@ enum aux_ch { enum intel_color_block { INTEL_PLANE_CB_PRE_CSC_LUT, INTEL_PLANE_CB_CSC, + INTEL_PLANE_CB_CSC_FF, INTEL_PLANE_CB_POST_CSC_LUT, INTEL_PLANE_CB_3DLUT, -- 2.25.1
