PRAMIN apertures are a crucial mechanism to direct read/write to VRAM. Add support for the same.
Cc: Nikola Djukic <[email protected]> Signed-off-by: Joel Fernandes <[email protected]> --- drivers/gpu/nova-core/mm.rs | 5 + drivers/gpu/nova-core/mm/pramin.rs | 293 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + drivers/gpu/nova-core/regs.rs | 6 + 4 files changed, 305 insertions(+) create mode 100644 drivers/gpu/nova-core/mm.rs create mode 100644 drivers/gpu/nova-core/mm/pramin.rs diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs new file mode 100644 index 000000000000..7a5dd4220c67 --- /dev/null +++ b/drivers/gpu/nova-core/mm.rs @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Memory management subsystems for nova-core. + +pub(crate) mod pramin; diff --git a/drivers/gpu/nova-core/mm/pramin.rs b/drivers/gpu/nova-core/mm/pramin.rs new file mode 100644 index 000000000000..707794f49add --- /dev/null +++ b/drivers/gpu/nova-core/mm/pramin.rs @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Direct VRAM access through the PRAMIN aperture. +//! +//! PRAMIN provides a 1MB sliding window into VRAM through BAR0, allowing the CPU to access +//! video memory directly. Access is managed through a two-level API: +//! +//! - [`Pramin`]: The parent object that owns the BAR0 reference and synchronization lock. +//! - [`PraminWindow`]: A guard object that holds exclusive PRAMIN access for its lifetime. +//! +//! The PRAMIN aperture is a 1MB region at BAR0 + 0x700000 for all GPUs. The window base is +//! controlled by the `NV_PBUS_BAR0_WINDOW` register and is 64KB aligned. +//! +//! # Examples +//! +//! ## Basic read/write +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::mm::pramin; +//! use kernel::devres::Devres; +//! use kernel::prelude::*; +//! use kernel::sync::Arc; +//! +//! fn example(devres_bar: Arc<Devres<Bar0>>, vram_region: core::ops::Range<u64>) -> Result<()> { +//! let pramin = Arc::pin_init(pramin::Pramin::new(devres_bar, vram_region)?, GFP_KERNEL)?; +//! let mut window = pramin.window()?; +//! +//! // Write and read back. +//! window.try_write32(0x100, 0xDEADBEEF)?; +//! let val = window.try_read32(0x100)?; +//! assert_eq!(val, 0xDEADBEEF); +//! +//! Ok(()) +//! } +//! ``` +//! +//! ## Auto-repositioning across VRAM regions +//! +//! ```no_run +//! use crate::driver::Bar0; +//! use crate::mm::pramin; +//! use kernel::devres::Devres; +//! use kernel::prelude::*; +//! use kernel::sync::Arc; +//! +//! fn example(devres_bar: Arc<Devres<Bar0>>, vram_region: core::ops::Range<u64>) -> Result<()> { +//! let pramin = Arc::pin_init(pramin::Pramin::new(devres_bar, vram_region)?, GFP_KERNEL)?; +//! let mut window = pramin.window()?; +//! +//! // Access first 1MB region. +//! window.try_write32(0x100, 0x11111111)?; +//! +//! // Access at 2MB - window auto-repositions. +//! window.try_write32(0x200000, 0x22222222)?; +//! +//! // Back to first region - window repositions again. +//! let val = window.try_read32(0x100)?; +//! assert_eq!(val, 0x11111111); +//! +//! Ok(()) +//! } +//! ``` + +#![expect(unused)] + +use core::ops::Range; + +use crate::{ + driver::Bar0, + num::IntoSafeCast, + regs, // +}; + +use kernel::{ + devres::Devres, + io::Io, + new_mutex, + prelude::*, + revocable::RevocableGuard, + sizes::{ + SZ_1M, + SZ_64K, // + }, + sync::{ + lock::mutex::MutexGuard, + Arc, + Mutex, // + }, +}; + +/// Target memory type for the BAR0 window register. +/// +/// Only VRAM is supported; Hopper+ GPUs do not support other targets. +#[repr(u8)] +#[derive(Debug, Default)] +pub(crate) enum Bar0WindowTarget { + /// Video RAM (GPU framebuffer memory). + #[default] + Vram = 0, +} + +impl From<Bar0WindowTarget> for u8 { + fn from(value: Bar0WindowTarget) -> Self { + value as u8 + } +} + +impl TryFrom<u8> for Bar0WindowTarget { + type Error = Error; + + fn try_from(value: u8) -> Result<Self> { + match value { + 0 => Ok(Self::Vram), + _ => Err(EINVAL), + } + } +} + +/// PRAMIN aperture base offset in BAR0. +const PRAMIN_BASE: usize = 0x700000; + +/// PRAMIN aperture size (1MB). +const PRAMIN_SIZE: usize = SZ_1M; + +/// Generate a PRAMIN read accessor. +macro_rules! define_pramin_read { + ($name:ident, $ty:ty) => { + #[doc = concat!("Read a `", stringify!($ty), "` from VRAM at the given offset.")] + pub(crate) fn $name(&mut self, vram_offset: usize) -> Result<$ty> { + let (bar_offset, new_base) = + self.compute_window(vram_offset, ::core::mem::size_of::<$ty>())?; + + if let Some(base) = new_base { + Self::write_window_base(&self.bar, base); + *self.state = base; + } + self.bar.$name(bar_offset) + } + }; +} + +/// Generate a PRAMIN write accessor. +macro_rules! define_pramin_write { + ($name:ident, $ty:ty) => { + #[doc = concat!("Write a `", stringify!($ty), "` to VRAM at the given offset.")] + pub(crate) fn $name(&mut self, vram_offset: usize, value: $ty) -> Result { + let (bar_offset, new_base) = + self.compute_window(vram_offset, ::core::mem::size_of::<$ty>())?; + + if let Some(base) = new_base { + Self::write_window_base(&self.bar, base); + *self.state = base; + } + self.bar.$name(value, bar_offset) + } + }; +} + +/// PRAMIN aperture manager. +/// +/// Call [`Pramin::window()`] to acquire exclusive PRAMIN access. +#[pin_data] +pub(crate) struct Pramin { + bar: Arc<Devres<Bar0>>, + /// Valid VRAM region. Accesses outside this range are rejected. + vram_region: Range<u64>, + /// PRAMIN aperture state, protected by a mutex. + /// + /// # Safety + /// + /// This lock is acquired during the DMA fence signaling critical path. + /// It must NEVER be held across any reclaimable CPU memory / allocations + /// (`GFP_KERNEL`), because the memory reclaim path can call + /// `dma_fence_wait()`, which would deadlock with this lock held. + #[pin] + state: Mutex<u64>, +} + +impl Pramin { + /// Create a pin-initializer for PRAMIN. + /// + /// `vram_region` specifies the valid VRAM address range. + pub(crate) fn new( + bar: Arc<Devres<Bar0>>, + vram_region: Range<u64>, + ) -> Result<impl PinInit<Self>> { + let bar_access = bar.try_access().ok_or(ENODEV)?; + let current_base = Self::read_window_base(&bar_access); + + Ok(pin_init!(Self { + bar, + vram_region, + state <- new_mutex!(current_base, "pramin_state"), + })) + } + + /// Acquire exclusive PRAMIN access. + /// + /// Returns a [`PraminWindow`] guard that provides VRAM read/write accessors. + /// The [`PraminWindow`] is exclusive and only one can exist at a time. + pub(crate) fn window(&self) -> Result<PraminWindow<'_>> { + let bar = self.bar.try_access().ok_or(ENODEV)?; + let state = self.state.lock(); + Ok(PraminWindow { + bar, + vram_region: self.vram_region.clone(), + state, + }) + } + + /// Read the current window base from the BAR0_WINDOW register. + fn read_window_base(bar: &Bar0) -> u64 { + let reg = regs::NV_PBUS_BAR0_WINDOW::read(bar); + // TODO: Convert to Bounded<u64, 40> when available. + u64::from(reg.window_base()) << 16 + } +} + +/// PRAMIN window guard for direct VRAM access. +/// +/// This guard holds exclusive access to the PRAMIN aperture. The window auto-repositions +/// when accessing VRAM offsets outside the current 1MB range. +/// +/// Only one [`PraminWindow`] can exist at a time per [`Pramin`] instance (enforced by the +/// internal `MutexGuard`). +pub(crate) struct PraminWindow<'a> { + bar: RevocableGuard<'a, Bar0>, + vram_region: Range<u64>, + state: MutexGuard<'a, u64>, +} + +impl PraminWindow<'_> { + /// Write a new window base to the BAR0_WINDOW register. + fn write_window_base(bar: &Bar0, base: u64) { + // CAST: The caller (compute_window) validates that base is within the + // VRAM region which is always <= 40 bits. After >> 16, a 40-bit base + // becomes 24 bits, which fits in u32. + regs::NV_PBUS_BAR0_WINDOW::default() + .set_target(Bar0WindowTarget::Vram) + .set_window_base((base >> 16) as u32) + .write(bar); + } + + /// Compute window parameters for a VRAM access. + /// + /// Returns (`bar_offset`, `new_base`) where: + /// - `bar_offset`: The BAR0 offset to use for the access. + /// - `new_base`: `Some(base)` if window needs repositioning, `None` otherwise. + fn compute_window( + &self, + vram_offset: usize, + access_size: usize, + ) -> Result<(usize, Option<u64>)> { + // Validate VRAM offset is within the valid VRAM region. + let vram_addr = vram_offset as u64; + let end_addr = vram_addr.checked_add(access_size as u64).ok_or(EINVAL)?; + if vram_addr < self.vram_region.start || end_addr > self.vram_region.end { + return Err(EINVAL); + } + + // Check if access fits within the current 1MB window. + let current_base = *self.state; + if vram_addr >= current_base { + let offset_in_window: usize = (vram_addr - current_base).into_safe_cast(); + if offset_in_window + access_size <= PRAMIN_SIZE { + return Ok((PRAMIN_BASE + offset_in_window, None)); + } + } + + // Access doesn't fit in current window - reposition. + // Hardware requires 64KB alignment for the window base register. + let needed_base = vram_addr & !(SZ_64K as u64 - 1); + let offset_in_window: usize = (vram_addr - needed_base).into_safe_cast(); + + // Verify access fits in the 1MB window from the new base. + if offset_in_window + access_size > PRAMIN_SIZE { + return Err(EINVAL); + } + + Ok((PRAMIN_BASE + offset_in_window, Some(needed_base))) + } + + define_pramin_read!(try_read8, u8); + define_pramin_read!(try_read16, u16); + define_pramin_read!(try_read32, u32); + define_pramin_read!(try_read64, u64); + + define_pramin_write!(try_write8, u8); + define_pramin_write!(try_write16, u16); + define_pramin_write!(try_write32, u32); + define_pramin_write!(try_write64, u64); +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nova_core.rs index b5caf1044697..c5a78d6388e5 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -13,6 +13,7 @@ mod gfw; mod gpu; mod gsp; +mod mm; mod num; mod regs; mod sbuffer; diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index ea0d32f5396c..8ec35b8c4b28 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -32,6 +32,7 @@ Architecture, Chipset, // }, + mm::pramin::Bar0WindowTarget, num::FromSafeCast, }; @@ -102,6 +103,11 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { 31:16 frts_err_code as u16; }); +register!(NV_PBUS_BAR0_WINDOW @ 0x00001700, "BAR0 window control for PRAMIN access" { + 25:24 target as u8 ?=> Bar0WindowTarget; + 23:0 window_base as u32, "Window base address (bits 39:16 of FB addr)"; +}); + // PFB // The following two registers together hold the physical system memory address that is used by the -- 2.34.1
