> Subject: [PATCH v2 17/24] drm/i915/lt_phy: Add .enable_clock hook on DDI > > Enable PLL clock on DDI by moving part of the PLL enabling sequence into a > DDI clock enabling function. > > Signed-off-by: Mika Kahola <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 ++++++++ > drivers/gpu/drm/i915/display/intel_lt_phy.c | 33 ++++++++++++------- > drivers/gpu/drm/i915/display/intel_lt_phy.h | 10 ++++-- > 4 files changed, 43 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 76ba308f32ad..51403d09c477 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -5298,7 +5298,7 @@ void intel_ddi_init(struct intel_display *display, > encoder->pipe_mask = ~0; > > if (HAS_LT_PHY(display)) { > - encoder->enable_clock = intel_xe3plpd_pll_enable; > + encoder->enable_clock = intel_xe3plpd_pll_enable_clock; > encoder->disable_clock = intel_xe3plpd_pll_disable; > encoder->port_pll_type = intel_mtl_port_pll_type; > encoder->get_config = xe3plpd_ddi_get_config; diff --git > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 412582e29ca6..54c7a255b3a5 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -4595,7 +4595,20 @@ static int xe3plpd_pll_get_freq(struct intel_display > *display, > return intel_lt_phy_calc_port_clock(display, &dpll_hw_state->ltpll); } > > +static void xe3plpd_pll_enable(struct intel_display *display, > + struct intel_dpll *pll, > + const struct intel_dpll_hw_state *dpll_hw_state) > { > + struct intel_encoder *encoder = get_intel_encoder(display, pll); > + > + if (drm_WARN_ON(display->drm, !encoder)) > + return; > + > + intel_xe3plpd_pll_enable(encoder, pll, dpll_hw_state); } > + > static const struct intel_dpll_funcs xe3plpd_pll_funcs = { > + .enable = xe3plpd_pll_enable, > .get_hw_state = xe3plpd_pll_get_hw_state, > .get_freq = xe3plpd_pll_get_freq, > }; > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c > b/drivers/gpu/drm/i915/display/intel_lt_phy.c > index c3686ac6adc9..6bc32d1734a7 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c > @@ -1883,9 +1883,11 @@ intel_lt_phy_enable_disable_tx(struct > intel_encoder *encoder, } > > void intel_lt_phy_pll_enable(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > + struct intel_dpll *pll, > + const struct intel_dpll_hw_state *dpll_hw_state) > { > struct intel_display *display = to_intel_display(encoder); > + int port_clock = intel_lt_phy_calc_port_clock(display, > +&dpll_hw_state->ltpll); > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > bool lane_reversal = dig_port->lane_reversal; > u8 owned_lane_mask = > intel_lt_phy_get_owned_lane_mask(encoder); > @@ -1901,11 +1903,11 @@ void intel_lt_phy_pll_enable(struct > intel_encoder *encoder, > wakeref = intel_lt_phy_transaction_begin(encoder); > > /* 1. Enable MacCLK at default 162 MHz frequency. */ > - intel_lt_phy_lane_reset(encoder, crtc_state->lane_count); > + intel_lt_phy_lane_reset(encoder, dpll_hw_state->ltpll.lane_count); > > /* 2. Program PORT_CLOCK_CTL register to configure clock muxes, > gating, and SSC. */ > - intel_lt_phy_program_port_clock_ctl(encoder, &crtc_state- > >dpll_hw_state.ltpll, > - crtc_state->port_clock, > lane_reversal); > + intel_lt_phy_program_port_clock_ctl(encoder, &dpll_hw_state->ltpll, > + port_clock, lane_reversal); > > /* 3. Change owned PHY lanes power to Ready state. */ > intel_lt_phy_powerdown_change_sequence(encoder, > owned_lane_mask, @@ -1915,12 +1917,12 @@ void > intel_lt_phy_pll_enable(struct intel_encoder *encoder, > * 4. Read the PHY message bus VDR register PHY_VDR_0_Config > check enabled PLL type, > * encoded rate and encoded mode. > */ > - if (intel_lt_phy_config_changed(encoder, &crtc_state- > >dpll_hw_state.ltpll)) { > + if (intel_lt_phy_config_changed(encoder, &dpll_hw_state->ltpll)) { > /* > * 5. Program the PHY internal PLL registers over PHY > message bus for the desired > * frequency and protocol type > */ > - intel_lt_phy_program_pll(encoder, &crtc_state- > >dpll_hw_state.ltpll); > + intel_lt_phy_program_pll(encoder, &dpll_hw_state->ltpll); > > /* 6. Use the P2P transaction flow */ > /* > @@ -1952,8 +1954,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder > *encoder, > * Change. We handle this step in bxt_set_cdclk(). > */ > /* 10. Program DDI_CLK_VALFREQ to match intended DDI > clock frequency. */ > - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), > - crtc_state->port_clock); > + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), > port_clock); > > /* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = > 1. */ > intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, > port), @@ -2000,7 +2001,7 @@ void intel_lt_phy_pll_enable(struct > intel_encoder *encoder, > lane_phy_pulse_status, > lane_phy_pulse_status); > } else { > - intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), > crtc_state->port_clock); > + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), > port_clock); > } > > /* > @@ -2011,7 +2012,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder > *encoder, > intel_lt_phy_powerdown_change_sequence(encoder, > owned_lane_mask, > XELPDP_P0_STATE_ACTIVE); > > - intel_lt_phy_enable_disable_tx(encoder, &crtc_state- > >dpll_hw_state.ltpll); > + intel_lt_phy_enable_disable_tx(encoder, &dpll_hw_state->ltpll); > intel_lt_phy_transaction_end(encoder, wakeref); } > > @@ -2282,14 +2283,22 @@ void intel_lt_phy_pll_state_verify(struct > intel_atomic_state *state, } > > void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state) > + struct intel_dpll *pll, > + const struct intel_dpll_hw_state *dpll_hw_state) { > + intel_lt_phy_pll_enable(encoder, pll, dpll_hw_state); } > + > +void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > { > struct intel_digital_port *dig_port = enc_to_dig_port(encoder); > > if (intel_tc_port_in_tbt_alt_mode(dig_port)) > intel_mtl_tbt_pll_enable_clock(encoder, crtc_state- > >port_clock); > else > - intel_lt_phy_pll_enable(encoder, crtc_state); > + /* TODO: remove when PLL mgr is in place. */ > + intel_xe3plpd_pll_enable(encoder, NULL, &crtc_state- > >dpll_hw_state); > } > > void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) diff --git > a/drivers/gpu/drm/i915/display/intel_lt_phy.h > b/drivers/gpu/drm/i915/display/intel_lt_phy.h > index 0053bb5489e5..9188ce980119 100644 > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h > @@ -11,13 +11,16 @@ > struct drm_printer; > struct intel_atomic_state; > struct intel_display; > +struct intel_dpll; > +struct intel_dpll_hw_state; > struct intel_encoder; > struct intel_crtc_state; > struct intel_crtc; > struct intel_lt_phy_pll_state; > > void intel_lt_phy_pll_enable(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state); > + struct intel_dpll *pll, > + const struct intel_dpll_hw_state *dpll_hw_state); > void intel_lt_phy_pll_disable(struct intel_encoder *encoder); int > intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, @@ -40,8 > +43,11 @@ int intel_lt_phy_calculate_hdmi_state(struct > intel_lt_phy_pll_state *lt_state, > u32 frequency_khz); > void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, > - const struct intel_crtc_state *crtc_state); > + struct intel_dpll *pll, > + const struct intel_dpll_hw_state *dpll_hw_state); > void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); void > intel_lt_phy_verify_plls(struct intel_display *display); > +void intel_xe3plpd_pll_enable_clock(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state); > > #endif /* __INTEL_LT_PHY_H__ */ > -- > 2.43.0
