Store number of rows and number of tables in intel_vbt_data when search for the VBT #57 succeeded.
Display version determines number of rows present in each table. pre-MTL platforms should have 10 rows while MTL+ should have 16 rows. Signed-off-by: Michał Grzelak <[email protected]> --- drivers/gpu/drm/i915/display/intel_bios.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_display_core.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 3f9e4d31c7375..d64668c1022a7 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2200,6 +2200,9 @@ parse_vswing_preemph_override(struct intel_display *display) return; drm_dbg_kms(display->drm, "VS/PE-O parsing not yet supported\n"); + + display->vbt.num_tables = block->num_tables; + display->vbt.num_rows = DISPLAY_VER(display) >= 14 ? 16 : 10; } static u8 translate_iboost(struct intel_display *display, u8 val) @@ -2997,6 +3000,10 @@ init_vbt_defaults(struct intel_display *display) !HAS_PCH_SPLIT(display)); drm_dbg_kms(display->drm, "Set default to SSC at %d kHz\n", display->vbt.lvds_ssc_freq); + + /* Vswing / Preemphasis Override */ + display->vbt.num_tables = 0; + display->vbt.num_rows = 0; } /* Common defaults which may be overridden by VBT. */ diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 76745ce6a716e..36ea4873deeb0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -242,6 +242,9 @@ struct intel_vbt_data { struct list_head display_devices; struct list_head bdb_blocks; + int num_tables; + int num_rows; + struct sdvo_device_mapping { u8 initialized; u8 dvo_port; -- 2.45.2
