On Thu, 07 May 2026, Michał Grzelak <[email protected]> wrote: > Variable naming of val and val1 should match register macro naming. > Historically, corresponding macros were named GEN6_PCODE_DATA and > GEN6_PCODE_DATA1. > > Rename register macro GEN6_PCODE_DATA to GEN6_PCODE_DATA0 since spec > appended '0' to the register name. Rename val into val0 in functions > declaring val1.
The changes to i915 and xe are completely independent. Please split. BR, Jani. > > Bspec: 19978 > > Changelog: > v2->v3 > - resolve conflict from rebase > > v1->v2 > - rebase onto drm-tip (Jani) > > Signed-off-by: Michał Grzelak <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_parent.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_parent.h | 2 +- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 2 +- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +- > drivers/gpu/drm/i915/intel_pcode.c | 14 +++++++------- > drivers/gpu/drm/i915/intel_pcode.h | 2 +- > drivers/gpu/drm/xe/display/xe_display_pcode.c | 4 ++-- > drivers/gpu/drm/xe/xe_pcode.c | 4 ++-- > drivers/gpu/drm/xe/xe_pcode.h | 2 +- > 10 files changed, 19 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_parent.c > b/drivers/gpu/drm/i915/display/intel_parent.c > index 67b21a42d354..7901b95ab114 100644 > --- a/drivers/gpu/drm/i915/display/intel_parent.c > +++ b/drivers/gpu/drm/i915/display/intel_parent.c > @@ -219,9 +219,9 @@ void intel_parent_pc8_unblock(struct intel_display > *display) > } > > /* pcode */ > -int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 > *val, u32 *val1) > +int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 > *val0, u32 *val1) > { > - return display->parent->pcode->read(display->drm, mbox, val, val1); > + return display->parent->pcode->read(display->drm, mbox, val0, val1); > } > > int intel_parent_pcode_write_timeout(struct intel_display *display, u32 > mbox, u32 val, int timeout_ms) > diff --git a/drivers/gpu/drm/i915/display/intel_parent.h > b/drivers/gpu/drm/i915/display/intel_parent.h > index 5f0c835b9416..f095ef900a10 100644 > --- a/drivers/gpu/drm/i915/display/intel_parent.h > +++ b/drivers/gpu/drm/i915/display/intel_parent.h > @@ -79,7 +79,7 @@ void intel_parent_pc8_block(struct intel_display *display); > void intel_parent_pc8_unblock(struct intel_display *display); > > /* pcode */ > -int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 > *val, u32 *val1); > +int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 > *val0, u32 *val1); > int intel_parent_pcode_write_timeout(struct intel_display *display, u32 > mbox, u32 val, int timeout_ms); > int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 > val); > int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 > request, > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index 9f61867e2478..22dd0179863e 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -1706,7 +1706,7 @@ static int mailbox_write(struct intel_vgpu *vgpu, > unsigned int offset, > { > u32 value = *(u32 *)p_data; > u32 cmd = value & 0xff; > - u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA); > + u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA0); > > switch (cmd) { > case GEN9_PCODE_READ_MEM_LATENCY: > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 64e906380131..d873072b7a92 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -697,7 +697,7 @@ > #define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7) > #define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3) > > -#define GEN6_PCODE_DATA _MMIO(0x138128) > +#define GEN6_PCODE_DATA0 _MMIO(0x138128) > #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 > #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 > #define GEN6_PCODE_DATA1 _MMIO(0x13812C) > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index de118fae0a49..25b72b20e709 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -611,7 +611,7 @@ static int iterate_generic_mmio(struct > intel_gvt_mmio_table_iter *iter) > MMIO_D(GEN6_UCGCTL1); > MMIO_D(GEN6_UCGCTL2); > MMIO_F(_MMIO(0x4f000), 0x90); > - MMIO_D(GEN6_PCODE_DATA); > + MMIO_D(GEN6_PCODE_DATA0); > MMIO_D(_MMIO(0x13812c)); > MMIO_D(GEN7_ERR_INT); > MMIO_D(HSW_EDRAM_CAP); > diff --git a/drivers/gpu/drm/i915/intel_pcode.c > b/drivers/gpu/drm/i915/intel_pcode.c > index c07d48fc1b35..1c9d1f413757 100644 > --- a/drivers/gpu/drm/i915/intel_pcode.c > +++ b/drivers/gpu/drm/i915/intel_pcode.c > @@ -58,7 +58,7 @@ static int gen7_check_mailbox_status(u32 mbox) > } > > static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox, > - u32 *val, u32 *val1, > + u32 *val0, u32 *val1, > int fast_timeout_us, int slow_timeout_ms, > bool is_read) > { > @@ -73,7 +73,7 @@ static int __snb_pcode_rw(struct intel_uncore *uncore, u32 > mbox, > if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) > return -EAGAIN; > > - intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val); > + intel_uncore_write_fw(uncore, GEN6_PCODE_DATA0, *val0); > intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0); > intel_uncore_write_fw(uncore, > GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); > @@ -87,7 +87,7 @@ static int __snb_pcode_rw(struct intel_uncore *uncore, u32 > mbox, > return -ETIMEDOUT; > > if (is_read) > - *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA); > + *val0 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA0); > if (is_read && val1) > *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1); > > @@ -97,12 +97,12 @@ static int __snb_pcode_rw(struct intel_uncore *uncore, > u32 mbox, > return gen6_check_mailbox_status(mbox); > } > > -int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 > *val1) > +int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val0, u32 > *val1) > { > int err; > > mutex_lock(&uncore->i915->sb_lock); > - err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true); > + err = __snb_pcode_rw(uncore, mbox, val0, val1, 500, 20, true); > mutex_unlock(&uncore->i915->sb_lock); > > if (err) { > @@ -278,11 +278,11 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 > mbcmd, u32 p1, u32 p2, u3 > return err; > } > > -static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 > *val1) > +static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val0, u32 > *val1) > { > struct drm_i915_private *i915 = to_i915(drm); > > - return snb_pcode_read(&i915->uncore, mbox, val, val1); > + return snb_pcode_read(&i915->uncore, mbox, val0, val1); > } > > static int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 > val, int timeout_ms) > diff --git a/drivers/gpu/drm/i915/intel_pcode.h > b/drivers/gpu/drm/i915/intel_pcode.h > index 19795ea8172e..deecc64bc1b3 100644 > --- a/drivers/gpu/drm/i915/intel_pcode.h > +++ b/drivers/gpu/drm/i915/intel_pcode.h > @@ -11,7 +11,7 @@ > struct drm_device; > struct intel_uncore; > > -int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 > *val1); > +int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val0, u32 > *val1); > int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val, > int timeout_ms); > #define snb_pcode_write(uncore, mbox, val) \ > snb_pcode_write_timeout((uncore), (mbox), (val), 1) > diff --git a/drivers/gpu/drm/xe/display/xe_display_pcode.c > b/drivers/gpu/drm/xe/display/xe_display_pcode.c > index f6820ef7e666..8dc9cbdb18ec 100644 > --- a/drivers/gpu/drm/xe/display/xe_display_pcode.c > +++ b/drivers/gpu/drm/xe/display/xe_display_pcode.c > @@ -6,12 +6,12 @@ > #include "xe_device.h" > #include "xe_pcode.h" > > -static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, > u32 *val1) > +static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 > *val0, u32 *val1) > { > struct xe_device *xe = to_xe_device(drm); > struct xe_tile *tile = xe_device_get_root_tile(xe); > > - return xe_pcode_read(tile, mbox, val, val1); > + return xe_pcode_read(tile, mbox, val0, val1); > } > > static int xe_display_pcode_write_timeout(struct drm_device *drm, u32 mbox, > u32 val, int timeout_ms) > diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c > index dc66d0c7ee06..37303ac09080 100644 > --- a/drivers/gpu/drm/xe/xe_pcode.c > +++ b/drivers/gpu/drm/xe/xe_pcode.c > @@ -132,12 +132,12 @@ int xe_pcode_write64_timeout(struct xe_tile *tile, u32 > mbox, u32 data0, u32 data > return err; > } > > -int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1) > +int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val0, u32 *val1) > { > int err; > > mutex_lock(&tile->pcode.lock); > - err = pcode_mailbox_rw(tile, mbox, val, val1, 1, true, false); > + err = pcode_mailbox_rw(tile, mbox, val0, val1, 1, true, false); > mutex_unlock(&tile->pcode.lock); > > return err; > diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h > index 490e4f269607..ccb5f71c78c6 100644 > --- a/drivers/gpu/drm/xe/xe_pcode.h > +++ b/drivers/gpu/drm/xe/xe_pcode.h > @@ -17,7 +17,7 @@ int xe_pcode_probe_early(struct xe_device *xe); > int xe_pcode_ready(struct xe_device *xe, bool locked); > int xe_pcode_init_min_freq_table(struct xe_tile *tile, u32 min_gt_freq, > u32 max_gt_freq); > -int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val, u32 *val1); > +int xe_pcode_read(struct xe_tile *tile, u32 mbox, u32 *val0, u32 *val1); > int xe_pcode_write_timeout(struct xe_tile *tile, u32 mbox, u32 val, > int timeout_ms); > int xe_pcode_write64_timeout(struct xe_tile *tile, u32 mbox, u32 data0, -- Jani Nikula, Intel
