From: Dibin Moolakadan Subrahmanian <[email protected]>
Program CMTG guardband to generate the Lower/Upper and early entry guardband indicators to the DMC for DC3co control. Signed-off-by: Dibin Moolakadan Subrahmanian <[email protected]> --- drivers/gpu/drm/i915/display/intel_cmtg.c | 25 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cmtg.h | 1 + .../gpu/drm/i915/display/intel_cmtg_regs.h | 8 ++++++ 3 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c index e70e4c0941d5..d1bce4150327 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.c +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -448,3 +448,28 @@ void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state) intel_cmtg_mask_interrupt(crtc_state, true); spin_unlock_irq(&display->irq.lock); } + +void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 breakeven_gb; + u32 dc5_exit_latency; + u32 line_time_us = 75; + u32 val; + + if (crtc_state->linetime) + line_time_us = DIV_ROUND_UP(crtc_state->linetime, 8); + + /* Break Even Guardband - DC3co Entry Latency / linetime )*/ + breakeven_gb = DIV_ROUND_UP(55, line_time_us); + + /* DC5 Exit Latency - DC3co Exit Latency / linetime ) */ + dc5_exit_latency = DIV_ROUND_UP(40, line_time_us); + + val = REG_FIELD_PREP(CMTG_HW_GB_BREAKEVEN_MASK, breakeven_gb) | + REG_FIELD_PREP(CMTG_HW_GB_DC5_EXIT_LATENCY_MASK, dc5_exit_latency) | + REG_FIELD_PREP(CMTG_HW_GB_UP_LW_BG_DIFF_MASK, 1); + + intel_de_write(display, CMTG_HW_GB(cpu_transcoder), val); +} diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h index 8fcb44d6398f..2c801a74acf9 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.h +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h @@ -23,5 +23,6 @@ void intel_cmtg_sanitize(struct intel_display *display); bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state); void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state); void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state); +void intel_cmtg_set_hwgb(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_CMTG_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h index 240a02cd4a3a..6404f763bd52 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h @@ -24,4 +24,12 @@ #define CMTG_SYNC_TO_PORT REG_BIT(29) #define CMTG_STATE REG_BIT(23) +#define _CMTG_HW_GB_A 0x6FA8C +#define _CMTG_HW_GB_B 0x6FB8C +#define CMTG_HW_GB(trans) _MMIO_TRANS((trans), \ + _CMTG_HW_GB_A, _CMTG_HW_GB_B) +#define CMTG_HW_GB_BREAKEVEN_MASK REG_GENMASK(11, 0) +#define CMTG_HW_GB_DC5_EXIT_LATENCY_MASK REG_GENMASK(27, 16) +#define CMTG_HW_GB_UP_LW_BG_DIFF_MASK REG_GENMASK(31, 28) + #endif /* __INTEL_CMTG_REGS_H__ */ -- 2.29.0
