Program CMTG link M/N.
Reviewed-by: Uma Shankar <[email protected]>
Signed-off-by: Animesh Manna <[email protected]>
---
drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
drivers/gpu/drm/i915/display/intel_cmtg.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
3 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 0a2d838319f9..d490c57ba8b7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -326,3 +326,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state
*crtc_state)
intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder),
vrr_ctl);
}
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cmtg_transcoder =
to_cmtg_transcoder(crtc_state->cpu_transcoder);
+ const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+ if (!intel_cmtg_is_allowed(crtc_state))
+ return;
+
+ intel_de_write(display, PIPE_DATA_M1(display, cmtg_transcoder),
m_n->link_m);
+ intel_de_write(display, PIPE_DATA_N1(display, cmtg_transcoder),
m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
struct intel_display;
struct intel_crtc_state;
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool
lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 701cb4f9d70d..dd53049898ea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1615,6 +1615,7 @@ static void hsw_configure_cpu_transcoder(const struct
intel_crtc_state *crtc_sta
&crtc_state->dp_m2_n2);
}
+ intel_cmtg_set_m_n(crtc_state);
intel_set_transcoder_timings(crtc_state);
if (cpu_transcoder != TRANSCODER_EDP)
--
2.29.0
