On Tue, 19 May 2026, Pranay Samala <[email protected]> wrote: > The integer lut programming loop never executes completely due to > incorrect condition (i++ > 130). > > Fix to properly program 129th+ entries for values > 1.0. > > Cc: <[email protected]> #v6.19 > Fixes: 82caa1c8813f ("drm/i915/color: Program Pre-CSC registers") > Signed-off-by: Pranay Samala <[email protected]> > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > Reviewed-by: Uma Shankar <[email protected]>
Okay, so this is a stable worthy fix, first sent 2½ months ago [1], and we're still tossing it around? Folks, there needs to be more urgency with obvious fixes like this. I see this was sent separately to intel-gfx and intel-xe [2] lists. The way to go is to just cross-post it. (Don't send it again, but do check the CI results for both.) BR, Jani. [1] https://lore.kernel.org/r/[email protected] [2] https://lore.kernel.org/r/[email protected] > --- > drivers/gpu/drm/i915/display/intel_color.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index 2d318e922671..3bfe09d81a4c 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -3976,7 +3976,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, > intel_de_write_dsb(display, dsb, > > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), > (1 << 24)); > - } while (i++ > 130); > + } while (i++ < 130); > } else { > for (i = 0; i < lut_size; i++) { > u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); -- Jani Nikula, Intel
