In intel_dsb_wait_for_delayed_vblank() the VRR path issues a WAIT_DSL_OUT(safe_window_start, vmin_safe_window_end) followed by a WAIT_USEC for SCL+1 scanlines to land on the delayed vblank.
Experimentally, when PIPEDSL is exactly at safe_window_start as the WAIT_DSL_OUT is reached, the wait is skipped and the DSB falls through immediately. The following WAIT_USEC then runs from too early a reference and the DSB interrupt (flip-done event) fires roughly one frame ahead of the delayed vblank. Wait one scanline first so PIPEDSL has moved into the window before WAIT_DSL_OUT runs. Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dsb.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index fec8a56e21ea..dae8ea33d069 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -902,7 +902,15 @@ void intel_dsb_wait_for_delayed_vblank(struct intel_atomic_state *state, * the hardware itself guarantees that we're SCL lines * away from the delayed vblank, and we won't be inside * the vmin safe window so this extra wait does nothing. + * + * Experimentally, when PIPEDSL is exactly at + * safe_window_start as the next WAIT_DSL_OUT is reached, + * the wait is skipped immediately. + * + * Wait one scanline first so PIPEDSL has moved into the + * window before WAIT_DSL_OUT runs. */ + intel_dsb_wait_usec(dsb, intel_scanlines_to_usecs(adjusted_mode, 1)); intel_dsb_wait_scanline_out(state, dsb, intel_vrr_safe_window_start(crtc_state), intel_vrr_vmin_safe_window_end(crtc_state)); -- 2.45.2
