From: Oscar Mateo <[email protected]>

Signed-off-by: Oscar Mateo <[email protected]>
---
 tests/.gitignore       |   1 +
 tests/Makefile.am      |   1 +
 tests/Makefile.sources |   1 +
 tests/gem_execlist.c   | 266 +++++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 269 insertions(+)
 create mode 100644 tests/gem_execlist.c

diff --git a/tests/.gitignore b/tests/.gitignore
index 019a0db..d360b20 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -37,6 +37,7 @@ gem_exec_lut_handle
 gem_exec_nop
 gem_exec_params
 gem_exec_parse
+gem_execlist
 gem_fd_exhaustion
 gem_fenced_exec_thrash
 gem_fence_thrash
diff --git a/tests/Makefile.am b/tests/Makefile.am
index e891bd8..074b8d7 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -49,6 +49,7 @@ gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_close_race_LDADD = $(LDADD) -lpthread
 gem_ctx_basic_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_ctx_basic_LDADD = $(LDADD) -lpthread
+gem_execlist_LDADD = $(LDADD) -lpthread
 gem_fence_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
 gem_fence_thrash_LDADD = $(LDADD) -lpthread
 gem_flink_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS)
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 6098a2b..fae7f97 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -31,6 +31,7 @@ TESTS_progs_M = \
        gem_exec_nop \
        gem_exec_params \
        gem_exec_parse \
+       gem_execlist \
        gem_fenced_exec_thrash \
        gem_fence_thrash \
        gem_flink \
diff --git a/tests/gem_execlist.c b/tests/gem_execlist.c
new file mode 100644
index 0000000..9916d6b
--- /dev/null
+++ b/tests/gem_execlist.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors: Oscar Mateo Lozano <[email protected]>
+ *
+ */
+
+#ifndef ANDROID
+#define _GNU_SOURCE
+#endif
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <time.h>
+#include <pthread.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_io.h"
+#include "intel_chipset.h"
+#include "ioctl_wrappers.h"
+
+/* options */
+int option_num_threads = 20;
+int option_num_iter = 100;
+
+static void
+emit_store_dword_imm(int ring_id, struct intel_batchbuffer *batch,
+                    drm_intel_bo *dest, uint32_t val)
+{
+       BEGIN_BATCH(4);
+       OUT_BATCH(MI_STORE_DWORD_IMM);
+       OUT_RELOC(dest, I915_GEM_DOMAIN_INSTRUCTION,
+                 I915_GEM_DOMAIN_INSTRUCTION, 0);
+       OUT_BATCH(0);
+       OUT_BATCH(val);
+       ADVANCE_BATCH();
+}
+
+static void send_one(int fd, int ring_id, bool ctx_create,
+                    drm_intel_bufmgr *bufmgr,
+                    struct intel_batchbuffer *batch,
+                    drm_intel_bo *target_buffer)
+{
+       int val;
+       uint32_t *buf;
+       drm_intel_context *context;
+
+       srand(time(NULL));
+       val = rand();
+
+       emit_store_dword_imm(ring_id, batch, target_buffer, val);
+       if (ctx_create) {
+               context = drm_intel_gem_context_create(bufmgr);
+               intel_batchbuffer_flush_with_context(batch, context);
+       } else
+               intel_batchbuffer_flush_on_ring(batch, ring_id);
+
+       drm_intel_bo_map(target_buffer, 0);
+
+       buf = target_buffer->virtual;
+       igt_assert_f(buf[0] == val,
+                    "value mismatch: current %d, expected %d\n",
+                    buf[0], val);
+
+       drm_intel_bo_unmap(target_buffer);
+
+       if (ctx_create)
+               drm_intel_gem_context_destroy(context);
+}
+
+static void send_multiple(int fd, int ring_id, bool ctx_create,
+                         drm_intel_bufmgr *bufmgr,
+                         struct intel_batchbuffer *batch,
+                         drm_intel_bo *target_buffer)
+{
+       int i, val = 0;
+       uint32_t *buf;
+       drm_intel_context *context;
+
+       srand(time(NULL));
+
+       if (ctx_create)
+               context = drm_intel_gem_context_create(bufmgr);
+
+       for (i = 0; i < option_num_iter; i++) {
+               val = rand();
+               if (ring_id < 0)
+                       ring_id = val%4 + 1;
+
+               emit_store_dword_imm(ring_id, batch, target_buffer, val);
+               if (ctx_create)
+                       intel_batchbuffer_flush_with_context(batch, context);
+               else
+                       intel_batchbuffer_flush_on_ring(batch, ring_id);
+       }
+
+       drm_intel_bo_map(target_buffer, 0);
+
+       buf = target_buffer->virtual;
+       igt_assert_f(buf[0] == val,
+                    "value mismatch: current %d, expected %d\n",
+                    buf[0], val);
+
+       drm_intel_bo_unmap(target_buffer);
+
+       if (ctx_create)
+               drm_intel_gem_context_destroy(context);
+}
+
+struct work_args {
+       int ring_id;
+       bool ctx_create;
+};
+
+static void *work_concurrent(void *arg)
+{
+       int fd, devid;
+       drm_intel_bufmgr *bufmgr;
+       struct intel_batchbuffer *batch;
+       drm_intel_bo *target_buffer;
+       struct work_args opts = *(struct work_args *)arg;
+
+       /* Initialize */
+       fd = drm_open_any();
+       igt_require(fd >= 0);
+
+       devid = intel_get_drm_devid(fd);
+
+       bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+       igt_assert(bufmgr);
+       drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+       batch = intel_batchbuffer_alloc(bufmgr, devid);
+       igt_assert(batch);
+
+       target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
+       igt_assert(target_buffer);
+
+       /* Work */
+       send_multiple(fd, opts.ring_id, opts.ctx_create,
+                       bufmgr, batch, target_buffer);
+
+       /* Cleanup */
+       drm_intel_bo_unreference(target_buffer);
+       intel_batchbuffer_free(batch);
+       drm_intel_bufmgr_destroy(bufmgr);
+
+       close(fd);
+
+       pthread_exit(NULL);
+}
+
+static void run_concurrent(int ring_id, int ctx_create)
+{
+       int i = 0;
+       void *retval;
+       pthread_t *threads = calloc(option_num_threads, sizeof(*threads));
+       struct work_args opts = {.ring_id = ring_id, .ctx_create = ctx_create};
+
+       for (i = 0; i < option_num_threads; i++)
+               pthread_create(&threads[i], NULL, work_concurrent, &opts);
+
+       for (i = 0; i < option_num_threads; i++)
+               igt_assert(pthread_join(threads[i], &retval) == 0);
+
+       free(threads);
+}
+
+static int fd;
+static int devid;
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+static drm_intel_bo *target_buffer;
+
+igt_main
+{
+       static const struct {
+               const char *name;
+               int ring;
+       } rings[] = {
+               { "default_ring", I915_EXEC_DEFAULT },
+               { "render", I915_EXEC_RENDER },
+               { "blitter", I915_EXEC_BLT },
+               { "video", I915_EXEC_BSD },
+               { "vebox", I915_EXEC_VEBOX },
+               { "random_ring", -1 },
+       };
+       int i;
+
+       igt_fixture {
+               fd = drm_open_any();
+               igt_require(fd >= 0);
+
+               devid = intel_get_drm_devid(fd);
+               igt_skip_on_f(intel_gen(devid) < 8,
+                               "No Country for Old Gen\n");
+
+               bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+               igt_assert(bufmgr);
+               drm_intel_bufmgr_gem_enable_reuse(bufmgr);
+
+               batch = intel_batchbuffer_alloc(bufmgr, devid);
+               igt_assert(batch);
+
+               target_buffer = drm_intel_bo_alloc(bufmgr,
+                               "target bo", 4096, 4096);
+               igt_assert(target_buffer);
+       }
+
+       for (i = 0; i < 5; i++) {
+               igt_subtest_f("one-%s", rings[i].name)
+                       send_one(fd, rings[i].ring, false, bufmgr,
+                                       batch, target_buffer);
+       }
+
+       for (i = 1; i < ARRAY_SIZE(rings); i++) {
+               igt_subtest_f("multiple-%s", rings[i].name)
+                       send_multiple(fd, rings[i].ring, false, bufmgr,
+                                       batch, target_buffer);
+
+               igt_subtest_f("concurrent-%s", rings[i].name)
+                       run_concurrent(rings[i].ring, false);
+       }
+
+       igt_subtest("multiple-render-context")
+               send_multiple(fd, I915_EXEC_RENDER, true,
+                               bufmgr, batch, target_buffer);
+
+       igt_subtest("concurrent-render-context")
+               run_concurrent(I915_EXEC_RENDER, true);
+
+       igt_fixture {
+               drm_intel_bo_unreference(target_buffer);
+               intel_batchbuffer_free(batch);
+               drm_intel_bufmgr_destroy(bufmgr);
+
+               close(fd);
+       }
+}
-- 
1.9.0

_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to