BIT 10 and BIT 11 is defined as RO bits set by HW , so mask these bits to avoid while writing and reading DC_STATE_EN to avaoid unnessory re writes.
BSpec: 69115 Signed-off-by: Dibin Moolakadan Subrahmanian <[email protected]> --- .../gpu/drm/i915/display/intel_display_power_well.c | 13 ++++++++++++- drivers/gpu/drm/i915/display/intel_display_regs.h | 3 +++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 0e7e6a2b1547..bba80e5e8b6f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -732,6 +732,17 @@ static void gen9_write_dc_state(struct intel_display *display, int rewrites = 0; int rereads = 0; u32 v; + u32 ro_mask = 0; + + /* + * mask the RO bits from state and read back to avoid + * unnecessary rewrites. + * FIXME: Implement RO mask for remaining display versions. + */ + if (DISPLAY_VER(display) >= 35) + ro_mask = DC_STATE_EN_RO_MASK; + + state = (state & ~ro_mask); intel_de_write(display, DC_STATE_EN, state); @@ -741,7 +752,7 @@ static void gen9_write_dc_state(struct intel_display *display, * we are confident that state is exactly what we want. */ do { - v = intel_de_read(display, DC_STATE_EN); + v = intel_de_read(display, DC_STATE_EN) & ~ro_mask; if (v != state) { intel_de_write(display, DC_STATE_EN, state); diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index d9efe5b0ba46..e58e53f1e2f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -3086,6 +3086,9 @@ enum skl_power_gate { #define DC_STATE_EN_UPTO_DC6 REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 2) #define DC_STATE_EN_UPTO_DC3CO REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 3) +/* Display ver 35+ */ +#define DC_STATE_EN_RO_MASK REG_GENMASK(11, 10) + #define DC_STATE_DEBUG _MMIO(0x45520) #define DC_STATE_DEBUG_MASK_CORES (1 << 0) #define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1) -- 2.43.0
