Pcode reports the number of subchannels for LPDDR4 and LPDDR5. But the page mask selection table is based on the channels. So adjust the number of channels for LPDDR4 and LPDDR5 so that the correct page mask can be picked. There are two subchannels per channel.
Bspec: 68871 Suggested-by: Ville Syrjala <[email protected]> Signed-off-by: Vinod Govindapillai <[email protected]> --- drivers/gpu/drm/i915/display/intel_display_power.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2e51dfcd5dce..758ce1287cac 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1614,12 +1614,18 @@ static void tgl_bw_buddy_init(struct intel_display *display) const struct dram_info *dram_info = intel_dram_info(display); const struct buddy_page_mask *table; unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; + u8 channels = dram_info->num_channels; int config, i; /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ if (display->platform.dgfx && !display->platform.dg1) return; + /* For LPDDR4 / LPDDR5, pcode reports subchannels. */ + if (dram_info->type == INTEL_DRAM_LPDDR4 || + dram_info->type == INTEL_DRAM_LPDDR5) + channels /= 2; + if (intel_display_wa(display, INTEL_DISPLAY_WA_1409767108)) /* Wa_1409767108 */ table = wa_1409767108_buddy_page_masks; @@ -1627,7 +1633,7 @@ static void tgl_bw_buddy_init(struct intel_display *display) table = tgl_buddy_page_masks; for (config = 0; table[config].page_mask != 0; config++) - if (table[config].num_channels == dram_info->num_channels && + if (table[config].num_channels == channels && table[config].type == dram_info->type) break; -- 2.43.0
