> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <[email protected]>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: [email protected]; [email protected]
> Cc: Manna, Animesh <[email protected]>; Shankar, Uma
> <[email protected]>
> Subject: [PATCH v4 04/13] drm/i915/display: Add DC3CO DC_STATE
> enable/disable support
>
> Add DC3CO handling to the dc_off power well sequencing and disable the
> DMC wakelock when exiting DC3CO.
>
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <[email protected]>
> Reviewed-by: Uma Shankar <[email protected]>
> ---
> .../drm/i915/display/intel_display_power_well.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 611f784d8a7a..3ea080d0e21e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -866,6 +866,13 @@ void gen9_set_dc_state(struct intel_display *display,
> u32 state)
> power_domains->dc_state = val & mask;
> }
>
> +static void xe3lpd_enable_dc3co(struct intel_display *display) {
Better to add a assert_can_enable_dc3co() which is followed for other dc-state
programming.
Regards,
Animesh
> + drm_dbg_kms(display->drm, "Enabling DC3CO\n");
> + intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
> + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO); }
> +
> static void assert_can_enable_dc5(struct intel_display *display) {
> enum i915_power_well_id high_pg;
> @@ -1054,9 +1061,13 @@ void gen9_disable_dc_states(struct intel_display
> *display)
> }
>
> if (old_state == DC_STATE_EN_UPTO_DC5 ||
> - old_state == DC_STATE_EN_UPTO_DC6)
> + old_state == DC_STATE_EN_UPTO_DC6 ||
> + old_state == DC_STATE_EN_UPTO_DC3CO)
> intel_dmc_wl_disable(display);
>
> + if (old_state == DC_STATE_EN_UPTO_DC3CO)
> + return;
> +
> intel_cdclk_get_cdclk(display, &cdclk_config);
> /* Can't read out voltage_level so can't use intel_cdclk_changed() */
> drm_WARN_ON(display->drm,
> @@ -1092,6 +1103,9 @@ static void gen9_dc_off_power_well_disable(struct
> intel_display *display,
> return;
>
> switch (power_domains->target_dc_state) {
> + case DC_STATE_EN_UPTO_DC3CO:
> + xe3lpd_enable_dc3co(display);
> + break;
> case DC_STATE_EN_UPTO_DC6:
> skl_enable_dc6(display);
> break;
> --
> 2.43.0
