On Wed, 3 Jun 2026, Kandpal, Suraj wrote:
Subject: [PATCH v5 2/8] drm/i915/bios: store VBT #57's metadata in
intel_vbt_data
Store tables, number of tables, number of rows and number of columns in
intel_vbt_data when search for the VBT #57 has succeeded. Structurize all
VS/PE-O relevant metadata inside anonymous struct named as vspeo.
Display version determines number of rows present in each table. pre-MTL
platforms should have 10 rows while MTL+ should have 16 rows.
v3->v4
- remove unnecessary init of VS/PE-O metadata (Suraj)
- add helper for computing number of rows (Suraj)
- fix num_rows's type (Jani, Suraj)
- declare num_rows (Suraj)
Signed-off-by: Michał Grzelak <[email protected]>
---
drivers/gpu/drm/i915/display/intel_bios.c | 10 +++++++++-
drivers/gpu/drm/i915/display/intel_display_core.h | 7 +++++++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 420b09b4d01ef..d071f0e5d4380 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2185,6 +2185,11 @@ parse_compression_parameters(struct
intel_display *display)
}
}
+static int vswing_preemph_num_rows(struct intel_display *display) {
+ return DISPLAY_VER(display) >= 14 ? 16 : 10; }
+
Bspec: 68963
Tells me that no of rows is not display version dependent rather it cares if we
Are using UHBR or not. DP 1.4 being 10 and DP 2.1 being 16
That is correct, but now I realized I haven't mentioned one thing yet. I
agree that it's not precisely display version dependant; and also DP1.4
should have 10 rows while D2.X should have 16. But it's because number
of row is dependant on the PHY type. I don't think there is any helper
for determining PHY type in intel_bios.c, the only I see is
intel_encoder_is_c10phy() from intel_cx0_phy.c but it operates on
intel_encoder. So as for now I am using this rough helper since it quite
strongly coincides with PHY types.
Will update commit message and add Bspec number.
BR,
Michał
Regards,
Suraj Kandpal
static void
parse_vswing_preemph_override(struct intel_display *display) { @@ -2199,7
+2204,10 @@ parse_vswing_preemph_override(struct intel_display *display)
if (!block)
return;
- drm_dbg_kms(display->drm, "valid VS/PE-O request but not yet
supported\n");
+ display->vbt.vspeo.tables = block->tables;
+ display->vbt.vspeo.num_tables = block->num_tables;
+ display->vbt.vspeo.num_columns = block->num_columns;
+ display->vbt.vspeo.num_rows = vswing_preemph_num_rows(display);
}
static u8 translate_iboost(struct intel_display *display, u8 val) diff --git
a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 09ce25a6d4b11..061bf479458f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -242,6 +242,13 @@ struct intel_vbt_data {
struct list_head display_devices;
struct list_head bdb_blocks;
+ struct {
+ const u32 *tables;
+ int num_tables;
+ int num_columns;
+ int num_rows;
+ } vspeo;
+
struct sdvo_device_mapping {
u8 initialized;
u8 dvo_port;
--
2.45.2
