This series adds initial DC3CO support for display version 35+ and adds debugfs visibility into DC3CO count/residency.
The series also includes required PSR/ALPM updates for DC3CO enablement. This series is based on the CMTG enablement series currently under review: https://patchwork.freedesktop.org/series/157664/ DC3CO is not enabled by this series since power_domains->allowed_dc_mask is not updated to include DC3CO. TODO: - Enable DC3CO in power_domains->allowed_dc_mask Changes in v2: - Move dc3co state from intel_atomic_state to display->power - Squash cleanup and related patches to reduce series from 19 to 13 patches Changes in v3: - Fix trigger always returning zero in intel_dc3co_compute_state(). Changes in v4: - Call intel_display_power_set_target_dc_state() only when DC3CO is supported. - Add as_sdp_supported check for Panel Replay trigger. - Add 1:1 pipe-port mapping check for display version 35 in intel_dc3co_port_pipe_compatible() and change dc3co eligibility compute logic. - Re-arm DC3CO work in PSR resume, and schedule it from intel_psr_post_plane_update() to cover cases where no PSR flush occurs. - Remove dc state validation that could break the fallback mechanism. - Keep dc5_reg initialization in the xe3lp debugfs to avoid invalid register access. Changes in v5: - Move dc3co functions to intel_display_power.c. - Add psr2_deep_sleep helper API. - Rename dc3co_eligible to dc3co_allowed - Add DC3CO compute and set target state in commit tail. Dibin Moolakadan Subrahmanian (14): drm/i915/display: Remove TGL DC3CO support drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding drm/i915/display: Use FIELD_PREP() for DC state enable bits drm/i915/display: Add DC3CO DC_STATE enable/disable support drm/i915/display: Add HAS_DC3CO() macro drm/i915/display: Add DC3CO support check drm/i915/psr: Add psr2 deep sleep helper API drm/i915/display: Add DC3CO compute and set target state in commit tail drm/i915/display: Store DC3CO eligibility in PSR state drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO drm/i915/display: Enable DC3CO idle protocol in ALPM drm/i915/display: PSR Add delayed work to exit DC3CO drm/i915/display: Add helper to enable DC counter drm/i915/display: Add DC3CO count and residency in dmc debugfs drivers/gpu/drm/i915/display/intel_alpm.c | 5 + drivers/gpu/drm/i915/display/intel_display.c | 14 +- .../gpu/drm/i915/display/intel_display_core.h | 2 + .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_power.c | 151 +++++++++- .../drm/i915/display/intel_display_power.h | 38 +++ .../i915/display/intel_display_power_well.c | 49 ++-- .../i915/display/intel_display_power_well.h | 1 + .../gpu/drm/i915/display/intel_display_regs.h | 14 +- .../drm/i915/display/intel_display_types.h | 7 +- drivers/gpu/drm/i915/display/intel_dmc.c | 16 +- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 + drivers/gpu/drm/i915/display/intel_dmc_wl.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 265 ++++++------------ drivers/gpu/drm/i915/display/intel_psr.h | 1 + drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 + 16 files changed, 351 insertions(+), 218 deletions(-) -- 2.43.0
