LT PHY PLL readout is only partially reliable, and the LT PHY code already documents that only a subset of the state can be read back reliably after power gating.
The generic pipe-state verification compares dpll_hw_state as part of intel_pipe_config_compare(), which can trigger false-positive "pipe state doesn't match!" warnings on LT PHY platforms. DPLL-specific verification already exists via intel_dpll_state_verify(). Skip the generic dpll_hw_state pipe-state compare on LT PHY platforms and rely on the dedicated DPLL verification path instead. Signed-off-by: Mika Kahola <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2fa10f858279..85ad2bc4963d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5374,8 +5374,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, if (display->dpll.mgr) PIPE_CONF_CHECK_P(intel_dpll); - /* FIXME convert everything over the dpll_mgr */ - if (display->dpll.mgr || HAS_GMCH(display)) + /* + * LT PHY PLL readout is only partially reliable and the PLL state + * is already verified via intel_dpll_state_verify(). Avoid false + * positives from the generic pipe state comparison. + */ + if ((display->dpll.mgr || HAS_GMCH(display)) && !HAS_LT_PHY(display)) PIPE_CONF_CHECK_PLL(dpll_hw_state); PIPE_CONF_CHECK_X(dsi_pll.ctrl); -- 2.43.0
