LRR already updates crtc_vtotal/crtc_vblank_end seamlessly.
Extend the same handling to crtc_vsync_start/crtc_vsync_end so
VSYNC timing changes are programmed and accepted via the LRR path instead
of forcing a full modeset.
v2: Add comment explaining why TRANS_VSYNC update is safe for DP LRR.
(Ville)
Signed-off-by: Ankit Nautiyal <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8e269b71f18e..90a0f3799476 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2816,6 +2816,16 @@ static void intel_set_transcoder_timings_lrr(const
struct intel_crtc_state *crtc
intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(crtc_vblank_start - 1) |
VBLANK_END(crtc_vblank_end - 1));
+
+ /*
+ * DP doesn't have vertical sync, so TRANS_VSYNC only affects
+ * the position of the vsync interrupt (and does so even when
+ * using the VRR timing generator!). Thus updating TRANS_VSYNC
+ * here seems fine even if it isn't double buffered.
+ */
+ intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
+ VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+ VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
/*
* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
* bits are not required. Since the support for these bits is going to
@@ -5189,9 +5199,9 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
if (!fastset || !allow_vblank_delay_fastset(current_config)) \
PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
- PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
- PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
if (!fastset || !pipe_config->update_lrr) { \
+ PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+ PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
PIPE_CONF_CHECK_I(name.crtc_vtotal); \
PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
} \
@@ -5805,6 +5815,8 @@ static bool lrr_params_changed(const struct
intel_crtc_state *old_crtc_state,
return old_adjusted_mode->crtc_vblank_start !=
new_adjusted_mode->crtc_vblank_start ||
old_adjusted_mode->crtc_vblank_end !=
new_adjusted_mode->crtc_vblank_end ||
+ old_adjusted_mode->crtc_vsync_start !=
new_adjusted_mode->crtc_vsync_start ||
+ old_adjusted_mode->crtc_vsync_end !=
new_adjusted_mode->crtc_vsync_end ||
old_adjusted_mode->crtc_vtotal !=
new_adjusted_mode->crtc_vtotal ||
old_crtc_state->set_context_latency !=
new_crtc_state->set_context_latency;
}
--
2.45.2
