This series is intended for CI validation only and is not intended for merging.
Please provide review feedback on the original patch series: * DC3CO: https://patchwork.freedesktop.org/series/163939/ * CMTG: https://patchwork.freedesktop.org/series/157664/ v2: - Rebase v3: - Rebase to dc3co v5 and cmtg v8. Animesh Manna (16): drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG drm/i915/cmtg: Set CMTG clock select drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info drm/i915/display: Pass target transcoder to intel_set_transcoder_timings() drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG transcoders drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr() drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings() drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder drm/i915/cmtg: Program VRR control register for CMTG transcoder drm/i915/cmtg: Set link M/N for CMTG transcoder drm/i915/cmtg: Add hook to enable CMTG with sync to port drm/i915/cmtg: Add a hook to make eDP transcoder secondary drm/i915/cmtg: Add CMTG interrupt handling drm/i915/cmtg: Add trigger to enable/disable cmtg drm/i915/cmtg: Restore CMTG after DC6 exit Dibin Moolakadan Subrahmanian (20): drm/i915/cmtg: Modify existing hook to disable CMTG drm/i915/cmtg: Add CMTG HWGB programming drm/i915/cmtg: Add CMTG scan line programming drm/i915/display: Remove TGL DC3CO support drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding drm/i915/display: Use FIELD_PREP() for DC state enable bits drm/i915/display: Add DC3CO DC_STATE enable/disable support drm/i915/display: Add HAS_DC3CO() macro drm/i915/display: Add DC3CO support check drm/i915/psr: Add psr2 deep sleep helper API drm/i915/display: Add DC3CO compute and set target state in commit tail drm/i915/display: Store DC3CO eligibility in PSR state drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO drm/i915/display: Enable DC3CO idle protocol in ALPM drm/i915/display: PSR Add delayed work to exit DC3CO drm/i915/display: Add helper to enable DC counter drm/i915/display: Add DC3CO count and residency in dmc debugfs drm/i915/display: Mask RO bits in gen9_write_dc_state() drm/i915/display: Guard CMTG function calls drm/i915/display: Enable DC3CO DC state drivers/gpu/drm/i915/display/intel_alpm.c | 5 + drivers/gpu/drm/i915/display/intel_cmtg.c | 274 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_cmtg.h | 14 + .../gpu/drm/i915/display/intel_cmtg_regs.h | 24 +- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 + drivers/gpu/drm/i915/display/intel_display.c | 110 ++++--- drivers/gpu/drm/i915/display/intel_display.h | 4 + .../gpu/drm/i915/display/intel_display_core.h | 2 + .../drm/i915/display/intel_display_device.c | 14 + .../drm/i915/display/intel_display_device.h | 3 +- .../gpu/drm/i915/display/intel_display_irq.c | 12 + .../drm/i915/display/intel_display_limits.h | 2 + .../drm/i915/display/intel_display_power.c | 172 ++++++++++- .../drm/i915/display/intel_display_power.h | 40 +++ .../i915/display/intel_display_power_well.c | 73 +++-- .../i915/display/intel_display_power_well.h | 1 + .../gpu/drm/i915/display/intel_display_regs.h | 16 +- .../drm/i915/display/intel_display_types.h | 11 +- drivers/gpu/drm/i915/display/intel_dmc.c | 16 +- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 + drivers/gpu/drm/i915/display/intel_dmc_wl.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 265 ++++++----------- drivers/gpu/drm/i915/display/intel_psr.h | 1 + drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 18 +- drivers/gpu/drm/i915/display/intel_vrr.h | 5 +- 26 files changed, 826 insertions(+), 272 deletions(-) -- 2.43.0
