From: Arun R Murthy <[email protected]> Add registers definitions for common SDP transmission line CMN_SDP_TL and CMN_SDP_TL_STGR_CTL.
v2: Move all registers to intel_dip_regs.h (Ankit) Bspec: 74384 Signed-off-by: Arun R Murthy <[email protected]> Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dip_regs.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h index 85dcbf42e77d..7e69c5cf63da 100644 --- a/drivers/gpu/drm/i915/display/intel_dip_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h @@ -14,4 +14,23 @@ #define EMP_AS_SDP_DB_TL_MASK REG_GENMASK(12, 0) #define EMP_AS_SDP_DB_TL(db_transmit_line) REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line)) +/* COMMON SDP TRANSMISSION LINE */ +#define _CMN_SDP_TL_A 0x6020c +#define CMN_SDP_TL(display, trans) _MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A) +#define TRANSMISSION_LINE_ENABLE REG_BIT(31) +#define BASE_TRANSMISSION_LINE_MASK REG_GENMASK(12, 0) +#define BASE_TRANSMISSION_LINE(x) REG_FIELD_PREP(BASE_TRANSMISSION_LINE_MASK, x) + +#define _CMN_SDP_TL_STGR_CTL_A 0x60214 +#define CMN_SDP_TL_STGR_CTL(display, trans) _MMIO_TRANS2(display, (trans), _CMN_SDP_TL_STGR_CTL_A) +#define VSC_EXT_STAGGER_MASK REG_GENMASK(11, 8) +#define VSC_EXT_STAGGER(x) REG_FIELD_PREP(VSC_EXT_STAGGER_MASK, x) +#define VSC_EXT_STAGGER_DEFAULT 0x2 +#define PPS_STAGGER_MASK REG_GENMASK(7, 4) +#define PPS_STAGGER(x) REG_FIELD_PREP(PPS_STAGGER_MASK, x) +#define PPS_STAGGER_DEFAULT 0x1 +#define GMP_STAGGER_MASK REG_GENMASK(3, 0) +#define GMP_STAGGER(x) REG_FIELD_PREP(GMP_STAGGER_MASK, x) +#define GMP_STAGGER_DEFAULT 0x0 + #endif /* __INTEL_DIP_REGS_H__ */ -- 2.45.2
