> Subject: [PATCH] drm/i915/mtl+: Enable PPS before PLL
>
> Enabling PPS after a display port's PLL is enabled leads to PLL / DDI BUF
> timeouts during system resuming after a long (> 45 mins) suspended state, at
> least on some ARL and MTL laptops, either all or some of them also containing
> an Nvidia GPU. Enabling PPS first and then the PLL fixes the problem for all
> the
> reporters.
>
> A similar issue is seen when enabling an external DP output on PHY B (vs. PHY
> A in the above eDP cases), where this change will not have any effect (since
> no
> PPS is used in that case). There isn't any direct connection between PPS and
> PLL, so the fix for eDP works by some side-effect only. However Bspec does
> seem to require enabling PPS first, so let's do that. Further investigation
> continues on the actual root cause and a cure for external panels.
>
> Fixes: 1a7fad2aea74 ("drm/i915/cx0: Enable dpll framework for MTL+")
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16098
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16064
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16042
> Cc: Mika Kahola <[email protected]>
> Cc: [email protected] # v7.0+
> Tested-by: Jouni Högander <[email protected]>
> Tested-by: Marco Nenciarini <[email protected]>
> Signed-off-by: Imre Deak <[email protected]>
LGTM,
Reviewed-by: Suraj Kandpal <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 2684e33b602d1..25314ec65ae77 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2652,9 +2652,6 @@ static void mtl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> /* 3. Select Thunderbolt */
> mtl_port_buf_ctl_io_selection(encoder);
>
> - /* 4. Enable Panel Power if PPS is required */
> - intel_pps_on(intel_dp);
> -
> /* 5. Enable the port PLL */
> intel_ddi_enable_clock(encoder, crtc_state);
>
> @@ -3710,6 +3707,14 @@ intel_ddi_pre_pll_enable(struct
> intel_atomic_state *state,
> else if (display->platform.geminilake || display->platform.broxton)
> bxt_dpio_phy_set_lane_optim_mask(encoder,
> crtc_state-
> >lane_lat_optim_mask);
> +
> + /*
> + * There is no direct connection between the PLL and PPS, however
> + * enabling PPS before PLL is required to avoid PLL/DDI BUF timeouts
> + * during system resume. Do that matching the Bspec order as well.
> + */
> + if (DISPLAY_VER(display) >= 14)
> + intel_pps_on(&dig_port->dp);
> }
>
> static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
> --
> 2.49.1
