On Xe3+, the SoC can lower the fabric frequency when the display needs less bandwidth than the minimum GV point. This threshold is defined as 20 GB/s. The driver can choose to request this threshold when the required data rate falls below it.
Add an extra QGV entry, with both peak bw and derated bw set to 20 GB/s, to the bandwidth info when all of the following hold: 1. The platform is Xe3+. 2. There is at least one existing QGV point. 3. The number of QGV points is below 8 (the maximum). Once a plane group is found, the driver iterates over all QGV points in that group to find the best match for the required data rate. If the required data rate is below 20 GB/s, it selects the peak bw from this new QGV point (20 GB/s). v2: add the peak bandwidth threshold as an additional QGV entry Bspec: 68880 Signed-off-by: Vinod Govindapillai <[email protected]> --- drivers/gpu/drm/i915/display/intel_bw.c | 33 +++++++++++++++++++ .../drm/i915/display/intel_display_device.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index db2ee9de5eec..71aa9a6928db 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -52,6 +52,8 @@ struct intel_qgv_point { #define DEPROGBWPCLIMIT 60 +#define PEAK_BW_THRESHOLD 20000 + struct intel_psf_gv_point { u8 clk; /* clock in multiples of 16.6666 MHz */ }; @@ -601,6 +603,34 @@ static int tgl_peakbw(int num_channels, int channel_width, int dclk) return num_channels * (channel_width / 8) * dclk; } +static void xe3_add_peakbw_threshold(struct intel_display *display) +{ + u8 qgv_points = display->bw.num_qgv_points; + + if (!HAS_PEAK_BW_THRESHOLD(display)) + return; + + if (qgv_points >= I915_NUM_QGV_POINTS) { + drm_warn(display->drm, "Maximum QGV points reached. Ignore the peak bw threshold\n"); + return; + } + + if (qgv_points <= 1) { + drm_warn(display->drm, "SAGV not supported. Ignore the peak bw threshold\n"); + return; + } + + display->bw.num_qgv_points++; + + display->bw.peakbw[qgv_points] = PEAK_BW_THRESHOLD; + + for (int i = 0; i < ARRAY_SIZE(display->bw.max); i++) + display->bw.max[i].deratedbw[qgv_points] = PEAK_BW_THRESHOLD; + + drm_dbg_kms(display->drm, "An extra QGV point %d added for Peak bw threshod of %d\n", + qgv_points, PEAK_BW_THRESHOLD); +} + static int tgl_get_bw_info(struct intel_display *display, const struct dram_info *dram_info, const struct intel_soc_bw_params *soc_bw_params, @@ -695,6 +725,9 @@ static int tgl_get_bw_info(struct intel_display *display, drm_dbg_kms(display->drm, "QGV %d: peakbw=%u\n", i, display->bw.peakbw[i]); } + /* For xe3 cases add an extra qgv point for Peak bw threshold */ + xe3_add_peakbw_threshold(display); + for (i = 0; i < qi.num_psf_points; i++) { const struct intel_psf_gv_point *sp = &qi.psf_points[i]; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 13e93a4b4f5f..1360a16edbc1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -191,6 +191,7 @@ struct intel_display_platforms { #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) +#define HAS_PEAK_BW_THRESHOLD(__display) (DISPLAY_VER(__display) >= 30) #define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12) #define HAS_PIXEL_NORMALIZER(__display) (DISPLAY_VER(__display) >= 35) #define HAS_PMDEMAND(__display) (DISPLAY_VER(__display) >= 14) -- 2.43.0
