From: Animesh Manna <[email protected]>

Make intel_set_transcoder_timings_lrr() take the target transcoder as an
explicit parameter instead of always using crtc_state->cpu_transcoder.
This allows the LRR timing programming sequence to be reused for other
transcoders (e.g. CMTG).

Move the intel_vrr_set_fixed_rr_timings() and intel_vrr_transcoder_enable()
calls out of intel_set_transcoder_timings_lrr() and into its only caller
intel_pipe_fastset(), so the helper now strictly programs the LRR timing
registers for the given transcoder.

No functional change intended.

v2:
- Add separate patch for renaming the cpu_transcoder variable. [Ville]

Reviewed-by: Uma Shankar <[email protected]>
Signed-off-by: Animesh Manna <[email protected]>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 8f8e24565a6d..049038742517 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2777,10 +2777,10 @@ static void intel_set_transcoder_timings(const struct 
intel_crtc_state *crtc_sta
        }
 }
 
-static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state 
*crtc_state)
+static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state 
*crtc_state,
+                                            enum transcoder cpu_transcoder)
 {
        struct intel_display *display = to_intel_display(crtc_state);
-       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
        const struct drm_display_mode *adjusted_mode = 
&crtc_state->hw.adjusted_mode;
        u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
 
@@ -2845,9 +2845,6 @@ static void intel_set_transcoder_timings_lrr(const struct 
intel_crtc_state *crtc
        intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
                       VACTIVE(crtc_vdisplay - 1) |
                       VTOTAL(crtc_vtotal - 1));
-
-       intel_vrr_set_fixed_rr_timings(crtc_state);
-       intel_vrr_transcoder_enable(crtc_state);
 }
 
 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
@@ -6694,8 +6691,11 @@ static void intel_pipe_fastset(const struct 
intel_crtc_state *old_crtc_state,
                intel_cpu_transcoder_set_m1_n1(crtc, 
new_crtc_state->cpu_transcoder,
                                               &new_crtc_state->dp_m_n);
 
-       if (new_crtc_state->update_lrr)
-               intel_set_transcoder_timings_lrr(new_crtc_state);
+       if (new_crtc_state->update_lrr) {
+               intel_set_transcoder_timings_lrr(new_crtc_state, 
new_crtc_state->cpu_transcoder);
+               intel_vrr_set_fixed_rr_timings(new_crtc_state);
+               intel_vrr_transcoder_enable(new_crtc_state);
+       }
 }
 
 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
-- 
2.43.0

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