Move CMRR register writes to fix refresh rate register write path to consolidate with fix refresh rate implementation.
Signed-off-by: Mitul Golani <[email protected]> --- drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index e36c0cab096a..5678c3a86796 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -329,6 +329,17 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state, if (!intel_vrr_possible(crtc_state)) return; + if (crtc_state->cmrr.enable) { + intel_de_write(display, TRANS_CMRR_M_HI(display, transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(display, TRANS_CMRR_M_LO(display, transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(display, TRANS_CMRR_N_HI(display, transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_n)); + intel_de_write(display, TRANS_CMRR_N_LO(display, transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_n)); + } + intel_de_write(display, TRANS_VRR_VMIN(display, transcoder), intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1); intel_de_write(display, TRANS_VRR_VMAX(display, transcoder), @@ -641,17 +652,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), - upper_32_bits(crtc_state->cmrr.cmrr_m)); - intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), - lower_32_bits(crtc_state->cmrr.cmrr_m)); - intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), - upper_32_bits(crtc_state->cmrr.cmrr_n)); - intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), - lower_32_bits(crtc_state->cmrr.cmrr_n)); - } - intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder); intel_cmtg_set_vrr_timings(crtc_state); -- 2.48.1
