On Mon, 18 May 2026, Mika Kahola wrote:
Prepare DG2 users to obtain clock state and reserve PLLs through the
shared DPLL framework.
Replace the DG2-specific compute hook with the generic framework-backed
helpers.
Assisted-by: Copilot:claude-sonnet-4-6
Signed-off-by: Mika Kahola <[email protected]>
Reviewed-by: Michał Grzelak <[email protected]>
BR,
Michał
---
drivers/gpu/drm/i915/display/intel_ddi.c | 28 ++++++++++++++++++++---
drivers/gpu/drm/i915/display/intel_dpll.c | 22 ++----------------
2 files changed, 27 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 86520848892e..b6799ed24de4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4307,11 +4307,33 @@ static void mtl_ddi_tc_phy_get_config(struct
intel_encoder *encoder,
mtl_port_to_pll_id(display,
encoder->port));
}
+static struct intel_dpll *dg2_ddi_get_pll(struct intel_encoder *encoder)
+{
+ struct intel_display *display = to_intel_display(encoder);
+
+ return intel_get_dpll_by_id(display, dg2_port_to_pll_id(encoder->port));
+}
+
static void dg2_ddi_get_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state)
{
- intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb);
- crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder,
&crtc_state->dpll_hw_state.mpllb);
+ struct icl_port_dpll *port_dpll =
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+ struct intel_dpll *pll = dg2_ddi_get_pll(encoder);
+
+ if (pll)
+ intel_ddi_get_clock(encoder, crtc_state, pll);
+
+ /*
+ * Keep the hw readout robust against unexpected NULL PLL lookups,
+ * so modeset verify always has intel_dpll populated for DG2.
+ */
+ if (!crtc_state->intel_dpll) {
+ port_dpll->pll = pll;
+ intel_mpllb_readout_hw_state(encoder,
&port_dpll->hw_state.mpllb);
+ icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+ crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder,
+
&port_dpll->hw_state.mpllb);
+ }
intel_ddi_get_config(encoder, crtc_state);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index f40807a5566b..20fd091cb9db 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -22,7 +22,6 @@
#include "intel_lvds_regs.h"
#include "intel_panel.h"
#include "intel_pps.h"
-#include "intel_snps_phy.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_sideband.h"
@@ -1194,24 +1193,6 @@ static int hsw_crtc_get_dpll(struct intel_atomic_state
*state,
return intel_dpll_reserve(state, crtc, encoder);
}
-static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
-{
- struct intel_crtc_state *crtc_state =
- intel_atomic_get_new_crtc_state(state, crtc);
- struct intel_encoder *encoder =
- intel_get_crtc_new_encoder(state, crtc_state);
- int ret;
-
- ret = intel_mpllb_calc_state(crtc_state, encoder);
- if (ret)
- return ret;
-
- crtc_state->hw.adjusted_mode.crtc_clock =
intel_crtc_dotclock(crtc_state);
-
- return 0;
-}
-
static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -1682,7 +1663,8 @@ static const struct intel_dpll_global_funcs
mtl_dpll_funcs = {
};
static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
- .crtc_compute_clock = dg2_crtc_compute_clock,
+ .crtc_compute_clock = hsw_crtc_compute_clock,
+ .crtc_get_dpll = hsw_crtc_get_dpll,
};
static const struct intel_dpll_global_funcs hsw_dpll_funcs = {
--
2.43.0
