On 7/8/2026 9:33 AM, Kandpal, Suraj wrote:
-----Original Message-----
From: Dibin Moolakadan Subrahmanian
<[email protected]>
Sent: Monday, July 6, 2026 9:01 PM
To: [email protected]; [email protected]
Cc: Kandpal, Suraj <[email protected]>
Subject: [PATCH] drm/i915/dmc: Enable PIPEDMC_ERROR interrupt on display
version 30+
Enable PIPEDMC_ERROR alongside the existing PIPEDMC_GTT_FAULT and
PIPEDMC_ATS_FAULT interrupt bits for display version 30+.
kms_pm_dc IGT test on PTL does not trigger the spurious interrupts that were
previously a concern.
This part about the IGT test can be omitted from commit message
Thanks for the review .
Will remove the IGT reference from commit message in the next version.
Enable the interrupt so pipe DMC errors are reported by
intel_pipedmc_irq_handler().
Bspec: 70296
Suggested-by: Suraj Kandpal <[email protected]>
Signed-off-by: Dibin Moolakadan Subrahmanian
<[email protected]>
With above fixed
LGTM,
Reviewed-by: Suraj Kandpal <[email protected]>
---
drivers/gpu/drm/i915/display/intel_dmc.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 11f5dbf91e68..a191eee240d9 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -505,14 +505,16 @@ static void pipedmc_clock_gating_wa(struct
intel_display *display, bool enable)
static u32 pipedmc_interrupt_mask(struct intel_display *display) {
- /*
- * TODO: Check if PIPEDMC_ERROR bit enabling causes errors
- * on PTL, enable it if validation passes
- */
if (DISPLAY_VER(display) >= 35)
return PIPEDMC_FLIPQ_PROG_DONE |
PIPEDMC_ERROR;
+ if (DISPLAY_VER(display) >= 30)
+ return PIPEDMC_FLIPQ_PROG_DONE |
+ PIPEDMC_GTT_FAULT |
+ PIPEDMC_ATS_FAULT |
+ PIPEDMC_ERROR;
+
/*
* FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B
* triggering it during the first DC state transition. Figure
--
2.43.0
